pci_config_get32

usr/src/uts/common/io/1394/adapters/hci1394_attach.c

464

global_swap = pci_config_get32(soft_state->pci_config,

usr/src/uts/common/io/1394/adapters/hci1394_attach.c

474

global_swap = pci_config_get32(soft_state->pci_config,

usr/src/uts/common/io/1394/adapters/hci1394_attach.c

548

global_swap = pci_config_get32(soft_state->pci_config,

usr/src/uts/common/io/aac/aac.c

2203

pci_config_get32(pci_config_handle, PCI_CONF_BASE0);

usr/src/uts/common/io/arn/arn_main.c

2857

val = pci_config_get32(sc->sc_cfg_handle, 0x40);

usr/src/uts/common/io/ath/ath_main.c

2039

val = pci_config_get32(asc->asc_cfg_handle, 0x40);

usr/src/uts/common/io/audio/drv/audiosolo/audiosolo.c

1210

data = pci_config_get32(dev->pcih, PCI_CONF_BASE2);

usr/src/uts/common/io/audio/drv/audiovia823x/audiovia823x.c

523

val = pci_config_get32(pcih, AUVIA_PCICFG);

usr/src/uts/common/io/bfe/bfe.c

963

bar_orig = pci_config_get32(bfe->bfe_conf_handle, BFE_BAR0_WIN);

usr/src/uts/common/io/bge/bge_chip2.c

203

regval = pci_config_get32(bgep->cfg_handle, regno);

usr/src/uts/common/io/bge/bge_chip2.c

243

val = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_RIADR);

usr/src/uts/common/io/bge/bge_chip2.c

3170

val32 = pci_config_get32

usr/src/uts/common/io/bge/bge_chip2.c

3217

mhcr = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_MHCR);

usr/src/uts/common/io/bge/bge_chip2.c

358

mhcr = pci_config_get32(handle, PCI_CONF_BGE_MHCR);

usr/src/uts/common/io/bge/bge_chip2.c

3652

(pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_MHCR) |

usr/src/uts/common/io/bge/bge_chip2.c

369

cidp->asic_rev_prod_id = pci_config_get32(handle, prodid);

usr/src/uts/common/io/bge/bge_chip2.c

372

cidp->businfo = pci_config_get32(handle, PCI_CONF_BGE_PCISTATE);

usr/src/uts/common/io/bge/bge_chip2.c

4232

regval = pci_config_get32(bgep->cfg_handle,

usr/src/uts/common/io/bge/bge_chip2.c

4854

mhcr = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_MHCR);

usr/src/uts/common/io/bge/bge_chip2.c

5500

regval = pci_config_get32(bgep->cfg_handle, regno);

usr/src/uts/common/io/bge/bge_chip2.c

6276

data = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR);

usr/src/uts/common/io/bge/bge_kstats.c

449

(knp++)->value.ui64 = pci_config_get32(handle, PCI_CONF_BGE_MHCR);

usr/src/uts/common/io/bge/bge_kstats.c

450

(knp++)->value.ui64 = pci_config_get32(handle, PCI_CONF_BGE_PDRWCR);

usr/src/uts/common/io/bge/bge_kstats.c

451

(knp++)->value.ui64 = pci_config_get32(handle, PCI_CONF_BGE_PCISTATE);

usr/src/uts/common/io/bge/bge_main2.c

3726

pci_state_reg = pci_config_get32(bgep->cfg_handle,

usr/src/uts/common/io/bnx/bnx_mm.c

103

*reg_value = pci_config_get32(udevp->os_param.pci_cfg_handle,

usr/src/uts/common/io/bnxe/bnxe_gld.c

993

pData->value = pci_config_get32(pUM->pPciCfg, (off_t)pData->offset);

usr/src/uts/common/io/bnxe/bnxe_mm.c

113

*pRegValue = pci_config_get32(pUM->pPciCfg, (off_t)pciReg);

usr/src/uts/common/io/cardbus/cardbus_cfg.c

1144

pci_config_get32(phdl->handle, phdl->io_decode_reg));

usr/src/uts/common/io/cardbus/cardbus_cfg.c

2714

request = pci_config_get32(config_handle,

usr/src/uts/common/io/cardbus/cardbus_cfg.c

2797

pci_config_get32(config_handle, 0x58),

usr/src/uts/common/io/cardbus/cardbus_cfg.c

2798

pci_config_get32(config_handle, 0x5c));

usr/src/uts/common/io/cardbus/cardbus_cfg.c

2802

pci_config_get32(config_handle, 0x60),

usr/src/uts/common/io/cardbus/cardbus_cfg.c

2803

pci_config_get32(config_handle, 0x64));

usr/src/uts/common/io/cardbus/cardbus_cfg.c

2807

pci_config_get32(config_handle, 0x68),

usr/src/uts/common/io/cardbus/cardbus_cfg.c

2808

pci_config_get32(config_handle, 0x6c));

usr/src/uts/common/io/cardbus/cardbus_cfg.c

2812

pci_config_get32(config_handle, 0x70),

usr/src/uts/common/io/cardbus/cardbus_cfg.c

2813

pci_config_get32(config_handle, 0x74));

usr/src/uts/common/io/cardbus/cardbus_cfg.c

2817

pci_config_get32(config_handle, 0x78),

usr/src/uts/common/io/cardbus/cardbus_cfg.c

2818

pci_config_get32(config_handle, 0x7c));

usr/src/uts/common/io/cardbus/cardbus_cfg.c

2955

request = pci_config_get32(config_handle, i);

usr/src/uts/common/io/cardbus/cardbus_cfg.c

3009

request = pci_config_get32(config_handle, PCI_CONF_ROM);

usr/src/uts/common/io/cardbus/cardbus_cfg.c

4350

pci_config_get32(config_handle, PCI_CONF_BASE0),

usr/src/uts/common/io/cardbus/cardbus_cfg.c

4351

pci_config_get32(config_handle, PCI_CONF_BASE1));

usr/src/uts/common/io/cardbus/cardbus_cfg.c

4354

pci_config_get32(config_handle, PCI_CONF_BASE2),

usr/src/uts/common/io/cardbus/cardbus_cfg.c

4355

pci_config_get32(config_handle, PCI_CONF_BASE3));

usr/src/uts/common/io/cardbus/cardbus_cfg.c

4358

pci_config_get32(config_handle, PCI_CONF_BASE4),

usr/src/uts/common/io/cardbus/cardbus_cfg.c

4359

pci_config_get32(config_handle, PCI_CONF_BASE5));

usr/src/uts/common/io/cardbus/cardbus_cfg.c

4362

pci_config_get32(config_handle, PCI_CONF_CIS),

usr/src/uts/common/io/cardbus/cardbus_cfg.c

4363

pci_config_get32(config_handle, PCI_CONF_ROM));

usr/src/uts/common/io/cardbus/cardbus_cfg.c

4389

pci_config_get32(config_handle, PCI_CBUS_SOCK_REG),

usr/src/uts/common/io/cardbus/cardbus_cfg.c

4421

pci_config_get32(config_handle, PCI_BCNF_PF_BASE_HIGH),

usr/src/uts/common/io/cardbus/cardbus_cfg.c

4422

pci_config_get32(config_handle, PCI_BCNF_PF_LIMIT_HIGH));

usr/src/uts/common/io/cardbus/cardbus_cfg.c

4429

pci_config_get32(config_handle, PCI_BCNF_ROM));

usr/src/uts/common/io/cardbus/cardbus_cfg.c

4434

pci_config_get32(config_handle, PCI_CBUS_MEM_BASE0),

usr/src/uts/common/io/cardbus/cardbus_cfg.c

4435

pci_config_get32(config_handle, PCI_CBUS_MEM_LIMIT0));

usr/src/uts/common/io/cardbus/cardbus_cfg.c

4438

pci_config_get32(config_handle, PCI_CBUS_MEM_BASE1),

usr/src/uts/common/io/cardbus/cardbus_cfg.c

4439

pci_config_get32(config_handle, PCI_CBUS_MEM_LIMIT1));

usr/src/uts/common/io/cardbus/cardbus_cfg.c

4442

pci_config_get32(config_handle, PCI_CBUS_IO_BASE0),

usr/src/uts/common/io/cardbus/cardbus_cfg.c

4443

pci_config_get32(config_handle, PCI_CBUS_IO_LIMIT0));

usr/src/uts/common/io/cardbus/cardbus_cfg.c

4446

pci_config_get32(config_handle, PCI_CBUS_IO_BASE1),

usr/src/uts/common/io/cardbus/cardbus_cfg.c

4447

pci_config_get32(config_handle, PCI_CBUS_IO_LIMIT1));

usr/src/uts/common/io/cardbus/cardbus_cfg.c

4467

pci_config_get32(config_handle, 0x80));

usr/src/uts/common/io/cardbus/cardbus_cfg.c

906

pci_config_get32(handle, offset), offset);

usr/src/uts/common/io/cardbus/cardbus_cfg.c

909

pci_config_get32(handle, offset + 4),

usr/src/uts/common/io/cardbus/cardbus_cfg.c

921

request = pci_config_get32(handle, offset);

usr/src/uts/common/io/cardbus/cardbus_cfg.c

934

pci_config_get32(handle, offset),

usr/src/uts/common/io/cardbus/cardbus_cfg.c

940

pci_config_get32(handle, offset+4),

usr/src/uts/common/io/cardbus/cardbus_cfg.c

946

pci_config_get32(handle, offset),

usr/src/uts/common/io/cardbus/cardbus_cfg.c

959

pci_config_get32(handle, offset), offset);

usr/src/uts/common/io/cardbus/cardbus_hp.c

1699

{ "BASE0 =", 0x10, CFG_GET(pci_config_get32), "%s 0x%08x" },

usr/src/uts/common/io/cardbus/cardbus_hp.c

1700

{ "BASE1 =", 0x14, CFG_GET(pci_config_get32), "%s 0x%08x" },

usr/src/uts/common/io/cardbus/cardbus_hp.c

1701

{ "BASE2 =", 0x18, CFG_GET(pci_config_get32), "%s 0x%08x" },

usr/src/uts/common/io/cardbus/cardbus_hp.c

1702

{ "BASE3 =", 0x1c, CFG_GET(pci_config_get32), "%s 0x%08x" },

usr/src/uts/common/io/cardbus/cardbus_hp.c

1703

{ "BASE4 =", 0x20, CFG_GET(pci_config_get32), "%s 0x%08x" },

usr/src/uts/common/io/cardbus/cardbus_hp.c

1704

{ "CIS Pointer =", 0x28, CFG_GET(pci_config_get32), "%s 0x%08x" },

usr/src/uts/common/io/cardbus/cardbus_hp.c

1717

{ "MemBase Addr=", 0x10, CFG_GET(pci_config_get32), "%s 0x%08x" },

usr/src/uts/common/io/cardbus/cardbus_hp.c

1722

{ "Mem0 Base =", 0x1c, CFG_GET(pci_config_get32), "%s 0x%08x" },

usr/src/uts/common/io/cardbus/cardbus_hp.c

1723

{ "Mem0 Limit =", 0x20, CFG_GET(pci_config_get32), "%s 0x%08x" },

usr/src/uts/common/io/cardbus/cardbus_hp.c

1724

{ "Mem1 Base =", 0x24, CFG_GET(pci_config_get32), "%s 0x%08x" },

usr/src/uts/common/io/cardbus/cardbus_hp.c

1725

{ "Mem1 Limit =", 0x28, CFG_GET(pci_config_get32), "%s 0x%08x" },

usr/src/uts/common/io/cardbus/cardbus_hp.c

1726

{ "I/O0 Base =", 0x2c, CFG_GET(pci_config_get32), "%s 0x%08x" },

usr/src/uts/common/io/cardbus/cardbus_hp.c

1727

{ "I/O0 Limit =", 0x30, CFG_GET(pci_config_get32), "%s 0x%08x" },

usr/src/uts/common/io/cardbus/cardbus_hp.c

1728

{ "I/O1 Base =", 0x34, CFG_GET(pci_config_get32), "%s 0x%08x" },

usr/src/uts/common/io/cardbus/cardbus_hp.c

1729

{ "I/O1 Limit =", 0x38, CFG_GET(pci_config_get32), "%s 0x%08x" },

usr/src/uts/common/io/cardbus/cardbus_hp.c

1733

{ "Legacy Addr =", 0x44, CFG_GET(pci_config_get32), "%s 0x%08x" },

usr/src/uts/common/io/chxge/ch.c

1996

v = pci_config_get32(chp->ch_hpci, 0x64);

usr/src/uts/common/io/chxge/ch.c

2004

v = pci_config_get32(chp->ch_hpci, 0x60);

usr/src/uts/common/io/chxge/glue.c

118

*val = pci_config_get32(obj->ch_hpci, reg);

usr/src/uts/common/io/chxge/glue.c

264

pe->pe_reg_val = reg = pci_config_get32(chp->ch_hpci, pe->addr);

usr/src/uts/common/io/chxge/glue.c

278

reg = pci_config_get32(chp->ch_hpci, pe->addr);

usr/src/uts/common/io/comstar/port/qlt/qlt.h

560

pci_config_get32(qlt->pcicfg_acc_handle, (off_t)(addr))

usr/src/uts/common/io/cxgbe/common/t4_hw.c

71

*val = pci_config_get32(sc->pci_regh, reg);

usr/src/uts/common/io/cxgbe/t4nex/t4_ioctl.c

89

r.value = pci_config_get32(sc->pci_regh, r.reg);

usr/src/uts/common/io/dmfe/dmfe_main.c

2461

regval = pci_config_get32(handle, PCI_CONF_COMM);

usr/src/uts/common/io/dmfe/dmfe_main.c

2464

regval = pci_config_get32(handle, PCI_DMFE_CONF_CFDD);

usr/src/uts/common/io/e1000g/e1000g_debug.c

427

pci_config_get32(handle, PCI_CONF_CIS));

usr/src/uts/common/io/e1000g/e1000g_debug.c

436

pci_config_get32(handle, PCI_CONF_ROM));

usr/src/uts/common/io/e1000g/e1000g_debug.c

495

pci_config_get32(handle, offset + PCI_MSI_ADDR_OFFSET));

usr/src/uts/common/io/e1000g/e1000g_debug.c

498

pci_config_get32(handle, offset + 0x8));

usr/src/uts/common/io/e1000g/e1000g_debug.c

519

pci_config_get32(handle, offset + PCIE_DEVCAP));

usr/src/uts/common/io/e1000g/e1000g_debug.c

528

pci_config_get32(handle, offset + PCIE_LINKCAP));

usr/src/uts/common/io/e1000g/e1000g_debug.c

542

uint32_t base = pci_config_get32(handle, offset);

usr/src/uts/common/io/e1000g/e1000g_debug.c

584

size = pci_config_get32(handle, offset);

usr/src/uts/common/io/fibre-channel/fca/qlc/ql_api.c

16461

return (pci_config_get32(ha->pci_handle, off));

usr/src/uts/common/io/fibre-channel/fca/qlge/qlge_dbg.c

664

pci_config_get32(qlge->pci_handle, PCI_CONF_BASE0);

usr/src/uts/common/io/fibre-channel/fca/qlge/qlge_dbg.c

667

pci_config_get32(qlge->pci_handle, PCI_CONF_BASE1);

usr/src/uts/common/io/fibre-channel/fca/qlge/qlge_dbg.c

670

pci_config_get32(qlge->pci_handle, PCI_CONF_BASE2);

usr/src/uts/common/io/fibre-channel/fca/qlge/qlge_dbg.c

673

pci_config_get32(qlge->pci_handle, PCI_CONF_BASE3);

usr/src/uts/common/io/fibre-channel/fca/qlge/qlge_dbg.c

676

pci_config_get32(qlge->pci_handle, PCI_CONF_BASE4);

usr/src/uts/common/io/fibre-channel/fca/qlge/qlge_dbg.c

685

pci_config_get32(qlge->pci_handle, PCI_CONF_ROM);

usr/src/uts/common/io/i2c/ctrl/pchsmbus/pchsmbus.c

1193

pch->ps_init_hcfg = pci_config_get32(pch->ps_cfg, PCH_R_PCIE_HCFG);

usr/src/uts/common/io/i2c/ctrl/pchsmbus/pchsmbus.c

391

uint32_t val = pci_config_get32(pch->ps_cfg, PCH_R_PCIE_HCFG);

usr/src/uts/common/io/i2c/ctrl/pchsmbus/pchsmbus.c

838

uint32_t val = pci_config_get32(pch->ps_cfg, PCH_R_PCIE_HCFG);

usr/src/uts/common/io/ib/adapters/hermon/hermon.c

3875

state->hs_cfg_data[i] = pci_config_get32(hdl, i << 2);

usr/src/uts/common/io/ib/adapters/hermon/hermon.c

3895

while ((pci_config_get32(hdl, 0) & 0x0000FFFF) != PCI_VENID_MLX) {

usr/src/uts/common/io/ib/adapters/hermon/hermon.c

3902

pci_config_get32(hdl, 0));

usr/src/uts/common/io/ib/adapters/hermon/hermon.c

4147

data32 = pci_config_get32(hdl,

usr/src/uts/common/io/ib/adapters/hermon/hermon.c

4150

data32 = pci_config_get32(hdl,

usr/src/uts/common/io/ib/adapters/hermon/hermon.c

4198

*data = pci_config_get32(hdl, vpd_data);

usr/src/uts/common/io/ib/adapters/hermon/hermon.c

4541

msix_data = pci_config_get32(hdl, offset);

usr/src/uts/common/io/ib/adapters/hermon/hermon.c

4546

msix_data = pci_config_get32(hdl, offset); /* table info */

usr/src/uts/common/io/ib/adapters/hermon/hermon.c

4552

msix_data = pci_config_get32(hdl, offset); /* PBA info */

usr/src/uts/common/io/ib/adapters/hermon/hermon.c

4935

pci_config_get32(pcihdl, i << 2);

usr/src/uts/common/io/ib/adapters/hermon/hermon.c

4951

while ((pci_config_get32(pcihdl, 0) & 0x0000FFFF) != PCI_VENID_MLX) {

usr/src/uts/common/io/ib/adapters/hermon/hermon_ioctl.c

2678

read = pci_config_get32(pci_config_hdl,

usr/src/uts/common/io/ib/adapters/hermon/hermon_ioctl.c

605

init_info.af_hwrev = pci_config_get32(pci_hdl,

usr/src/uts/common/io/ib/adapters/tavor/tavor.c

2335

state->ts_cfg_data[i] = pci_config_get32(hdl, i << 2);

usr/src/uts/common/io/ib/adapters/tavor/tavor.c

2357

pci_config_get32(phdl, i << 2);

usr/src/uts/common/io/ib/adapters/tavor/tavor.c

2382

while (pci_config_get32(phdl, 0) == TAVOR_SW_RESET_NOTDONE) {

usr/src/uts/common/io/ib/adapters/tavor/tavor.c

2417

while (pci_config_get32(hdl, 0) == TAVOR_SW_RESET_NOTDONE) {

usr/src/uts/common/io/ib/adapters/tavor/tavor.c

2646

*data = pci_config_get32(hdl, vpd_data);

usr/src/uts/common/io/ib/adapters/tavor/tavor.c

2769

status = pci_config_get32(hdl, offset + 4);

usr/src/uts/common/io/ib/adapters/tavor/tavor_ioctl.c

1970

read = pci_config_get32(pci_config_hdl, TAVOR_HW_FLASH_CFG_DATA);

usr/src/uts/common/io/ib/adapters/tavor/tavor_ioctl.c

531

init_info.tf_hwrev = pci_config_get32(state->ts_pci_cfghdl,

usr/src/uts/common/io/igb/igb_debug.c

102

pci_config_get32(handle, PCI_CONF_BASE1));

usr/src/uts/common/io/igb/igb_debug.c

105

pci_config_get32(handle, PCI_CONF_BASE2));

usr/src/uts/common/io/igb/igb_debug.c

108

msix_bar = pci_config_get32(handle, PCI_CONF_BASE3);

usr/src/uts/common/io/igb/igb_debug.c

114

pci_config_get32(handle, PCI_CONF_BASE4));

usr/src/uts/common/io/igb/igb_debug.c

117

pci_config_get32(handle, PCI_CONF_BASE5));

usr/src/uts/common/io/igb/igb_debug.c

120

pci_config_get32(handle, PCI_CONF_CIS));

usr/src/uts/common/io/igb/igb_debug.c

129

pci_config_get32(handle, PCI_CONF_ROM));

usr/src/uts/common/io/igb/igb_debug.c

188

pci_config_get32(handle, offset + PCI_MSI_ADDR_OFFSET));

usr/src/uts/common/io/igb/igb_debug.c

191

pci_config_get32(handle, offset + 0x8));

usr/src/uts/common/io/igb/igb_debug.c

212

tbl_offset = pci_config_get32(handle, offset + PCI_MSIX_TBL_OFFSET);

usr/src/uts/common/io/igb/igb_debug.c

220

pba_offset = pci_config_get32(handle, offset + PCI_MSIX_PBA_OFFSET);

usr/src/uts/common/io/igb/igb_debug.c

244

pci_config_get32(handle, offset + PCIE_DEVCAP));

usr/src/uts/common/io/igb/igb_debug.c

253

pci_config_get32(handle, offset + PCIE_LINKCAP));

usr/src/uts/common/io/igb/igb_debug.c

99

pci_config_get32(handle, PCI_CONF_BASE0));

usr/src/uts/common/io/iwn/if_iwn.c

5330

reg = pci_config_get32(sc->sc_pcih,

usr/src/uts/common/io/iwn/if_iwn.c

7113

reg = pci_config_get32(sc->sc_pcih,

usr/src/uts/common/io/ixgbe/ixgbe_debug.c

224

pci_config_get32(handle, PCI_CONF_BASE0));

usr/src/uts/common/io/ixgbe/ixgbe_debug.c

227

pci_config_get32(handle, PCI_CONF_BASE1));

usr/src/uts/common/io/ixgbe/ixgbe_debug.c

230

pci_config_get32(handle, PCI_CONF_BASE2));

usr/src/uts/common/io/ixgbe/ixgbe_debug.c

233

msix_bar = pci_config_get32(handle, PCI_CONF_BASE3);

usr/src/uts/common/io/ixgbe/ixgbe_debug.c

239

pci_config_get32(handle, PCI_CONF_BASE4));

usr/src/uts/common/io/ixgbe/ixgbe_debug.c

242

pci_config_get32(handle, PCI_CONF_BASE5));

usr/src/uts/common/io/ixgbe/ixgbe_debug.c

245

pci_config_get32(handle, PCI_CONF_CIS));

usr/src/uts/common/io/ixgbe/ixgbe_debug.c

254

pci_config_get32(handle, PCI_CONF_ROM));

usr/src/uts/common/io/ixgbe/ixgbe_debug.c

313

pci_config_get32(handle, offset + PCI_MSI_ADDR_OFFSET));

usr/src/uts/common/io/ixgbe/ixgbe_debug.c

316

pci_config_get32(handle, offset + 0x8));

usr/src/uts/common/io/ixgbe/ixgbe_debug.c

337

tbl_offset = pci_config_get32(handle, offset + PCI_MSIX_TBL_OFFSET);

usr/src/uts/common/io/ixgbe/ixgbe_debug.c

345

pba_offset = pci_config_get32(handle, offset + PCI_MSIX_PBA_OFFSET);

usr/src/uts/common/io/ixgbe/ixgbe_debug.c

369

pci_config_get32(handle, offset + PCIE_DEVCAP));

usr/src/uts/common/io/ixgbe/ixgbe_debug.c

378

pci_config_get32(handle, offset + PCIE_LINKCAP));

usr/src/uts/common/io/mega_sas/megaraid_sas.c

459

instance->baseaddress = pci_config_get32(

usr/src/uts/common/io/mr_sas/mr_sas.c

616

instance->baseaddress = pci_config_get32(

usr/src/uts/common/io/myri10ge/drv/myri10ge.c

5638

pci_config_get32(handle, ptr + PCI_MSI_ADDR_OFFSET);

usr/src/uts/common/io/myri10ge/drv/myri10ge.c

5640

pci_config_get32(handle, ptr + PCI_MSI_ADDR_OFFSET + 4);

usr/src/uts/common/io/myri10ge/drv/myri10ge.c

5687

pci_config_get32(handle, i*4);

usr/src/uts/common/io/myri10ge/drv/myri10ge.c

5801

csr = pci_config_get32(handle, PCI_CONF_COMM);

usr/src/uts/common/io/nge/nge_chip.c

130

regval = pci_config_get32(ngep->cfg_handle, regno);

usr/src/uts/common/io/nge/nge_chip.c

619

interbus_conf.conf_val = pci_config_get32(handle,

usr/src/uts/common/io/nge/nge_chip.c

633

pci_config_get32(handle, PCI_CONF_HT_MSI_MASK);

usr/src/uts/common/io/nge/nge_chip.c

647

pci_config_get32(handle, PCI_CONF_HT_MSI_MAP_CAP);

usr/src/uts/common/io/nge/nge_chip.c

653

interbus_conf.conf_val = pci_config_get32(handle,

usr/src/uts/common/io/ntxn/unm_gem.c

1114

control = pci_config_get32(pcihdl, 0xD0);

usr/src/uts/common/io/ntxn/unm_gem.c

1119

control = pci_config_get32(pcihdl, 0xC8);

usr/src/uts/common/io/ntxn/unm_gem.c

1120

control = pci_config_get32(pcihdl, 0xC8);

usr/src/uts/common/io/ntxn/unm_gem.c

367

pexsizes = pci_config_get32(pci_cfg_hdl, 0xd8);

usr/src/uts/common/io/ntxn/unm_nic_main.c

1942

*ptr4 = (int)pci_config_get32(conf_handle, data.off);

usr/src/uts/common/io/nxge/nxge_main.c

7087

rvalue = pci_config_get32(nxgep->dev_regs->nxge_pciregh,

usr/src/uts/common/io/nxge/nxge_main.c

7137

value = (pci_config_get32(dev_regs->nxge_pciregh,

usr/src/uts/common/io/nxge/nxge_main.c

7144

pci_config_get32(dev_regs->nxge_pciregh,

usr/src/uts/common/io/nxge/nxge_main.c

7153

pci_config_get32(dev_regs->nxge_pciregh,

usr/src/uts/common/io/pci_cap.c

107

if ((xcaps_hdr = pci_config_get32(h, base)) == PCI_CAP_EINVAL32)

usr/src/uts/common/io/pci_cap.c

188

if ((xcaps_hdr = pci_config_get32(h, base)) == PCI_CAP_EINVAL32)

usr/src/uts/common/io/pci_cap.c

287

data = pci_config_get32(h, offset);

usr/src/uts/common/io/pci_cap.c

352

if ((*ptr++ = pci_config_get32(h, base)) == PCI_CAP_EINVAL32)

usr/src/uts/common/io/pci_cap.c

95

if ((xcaps_hdr = pci_config_get32(h, base)) == PCI_CAP_EINVAL32)

usr/src/uts/common/io/pciex/hotplug/pciehpc.c

1166

return (pci_config_get32(bus_p->bus_cfg_hdl, off));

usr/src/uts/common/io/pciex/hotplug/pcishpc.c

174

pci_config_get32(bus_p->bus_cfg_hdl, i));

usr/src/uts/common/io/pciex/hotplug/pcishpc.c

2378

return (pci_config_get32(bus_p->bus_cfg_hdl,

usr/src/uts/common/io/pciex/pci_props.c

333

return (pci_config_get32(acc, off));

usr/src/uts/common/io/pciex/pcieb.c

432

bus_dev_ven_id = pci_config_get32(cfg_hdl, PCI_CONF_VENID);

usr/src/uts/common/io/qede/qede_gld.c

1356

ret = pci_config_get32(qede->pci_cfg_handle, addr);

usr/src/uts/common/io/qede/qede_osal.c

624

*val = pci_config_get32(qede->pci_cfg_handle, (off_t)addr);

usr/src/uts/common/io/rge/rge_chip.c

1679

regval = pci_config_get32(rgep->cfg_handle, regno);

usr/src/uts/common/io/sata/adapters/nv_sata/nv_sata.c

2566

reg32 = pci_config_get32(pci_conf_handle,

usr/src/uts/common/io/sata/adapters/nv_sata/nv_sata.c

2579

reg32 = pci_config_get32(pci_conf_handle,

usr/src/uts/common/io/sata/adapters/nv_sata/nv_sata.c

2610

reg32 = pci_config_get32(pci_conf_handle, NV_SATA_CFG_42);

usr/src/uts/common/io/sata/adapters/nv_sata/nv_sata.c

2667

reg32 = pci_config_get32(pci_conf_handle, NV_SATA_CFG_20);

usr/src/uts/common/io/sata/adapters/nv_sata/nv_sata.c

6625

*cbpp = pci_config_get32(pci_conf_handle, SGPIO_CBP);

usr/src/uts/common/io/sata/adapters/nv_sata/nv_sata.c

829

reg32 = pci_config_get32(pci_conf_handle, NV_SATA_CFG_20);

usr/src/uts/common/io/scsi/adapters/pmcs/pmcs_fwlog.c

746

pci_config_get32(pwp->pci_acc_handle, PCI_CONF_REVID));

usr/src/uts/common/io/scsi/adapters/pmcs/pmcs_fwlog.c

749

pci_config_get32(pwp->pci_acc_handle, PCI_CONF_CACHE_LINESZ));

usr/src/uts/common/io/scsi/adapters/pmcs/pmcs_fwlog.c

751

pci_config_get32(pwp->pci_acc_handle, PCI_CONF_BASE0));

usr/src/uts/common/io/scsi/adapters/pmcs/pmcs_fwlog.c

753

pci_config_get32(pwp->pci_acc_handle, PCI_CONF_BASE1));

usr/src/uts/common/io/scsi/adapters/pmcs/pmcs_fwlog.c

755

pci_config_get32(pwp->pci_acc_handle, PCI_CONF_BASE2));

usr/src/uts/common/io/scsi/adapters/pmcs/pmcs_fwlog.c

757

pci_config_get32(pwp->pci_acc_handle, PCI_CONF_BASE3));

usr/src/uts/common/io/scsi/adapters/pmcs/pmcs_fwlog.c

759

pci_config_get32(pwp->pci_acc_handle, PCI_CONF_BASE4));

usr/src/uts/common/io/scsi/adapters/pmcs/pmcs_fwlog.c

761

pci_config_get32(pwp->pci_acc_handle, PCI_CONF_BASE5));

usr/src/uts/common/io/scsi/adapters/pmcs/pmcs_fwlog.c

763

pci_config_get32(pwp->pci_acc_handle, PCI_CONF_SUBVENID));

usr/src/uts/common/io/scsi/adapters/pmcs/pmcs_fwlog.c

765

pci_config_get32(pwp->pci_acc_handle, PCI_CONF_ROM));

usr/src/uts/common/io/scsi/adapters/pmcs/pmcs_fwlog.c

770

pci_config_get32(pwp->pci_acc_handle, PCI_CONF_ILINE));

usr/src/uts/common/io/scsi/adapters/pmcs/pmcs_fwlog.c

772

"0x%08x\n", pci_config_get32(pwp->pci_acc_handle, PMCS_PCI_PMC));

usr/src/uts/common/io/scsi/adapters/pmcs/pmcs_fwlog.c

774

pci_config_get32(pwp->pci_acc_handle, PMCS_PCI_PMCSR));

usr/src/uts/common/io/scsi/adapters/pmcs/pmcs_fwlog.c

777

pci_config_get32(pwp->pci_acc_handle, PMCS_PCI_MSI));

usr/src/uts/common/io/scsi/adapters/pmcs/pmcs_fwlog.c

779

pci_config_get32(pwp->pci_acc_handle, PMCS_PCI_MAL));

usr/src/uts/common/io/scsi/adapters/pmcs/pmcs_fwlog.c

781

pci_config_get32(pwp->pci_acc_handle, PMCS_PCI_MAU));

usr/src/uts/common/io/scsi/adapters/pmcs/pmcs_fwlog.c

786

pci_config_get32(pwp->pci_acc_handle, PMCS_PCI_PCIE));

usr/src/uts/common/io/scsi/adapters/pmcs/pmcs_fwlog.c

788

pci_config_get32(pwp->pci_acc_handle, PMCS_PCI_DEV_CAP));

usr/src/uts/common/io/scsi/adapters/pmcs/pmcs_fwlog.c

791

pci_config_get32(pwp->pci_acc_handle, PMCS_PCI_DEV_CTRL));

usr/src/uts/common/io/scsi/adapters/pmcs/pmcs_fwlog.c

793

pci_config_get32(pwp->pci_acc_handle, PMCS_PCI_LINK_CAP));

usr/src/uts/common/io/scsi/adapters/pmcs/pmcs_fwlog.c

796

pci_config_get32(pwp->pci_acc_handle, PMCS_PCI_LINK_CTRL));

usr/src/uts/common/io/scsi/adapters/pmcs/pmcs_fwlog.c

798

pci_config_get32(pwp->pci_acc_handle, PMCS_PCI_MSIX_CAP));

usr/src/uts/common/io/scsi/adapters/pmcs/pmcs_fwlog.c

800

pci_config_get32(pwp->pci_acc_handle, PMCS_PCI_TBL_OFFSET));

usr/src/uts/common/io/scsi/adapters/pmcs/pmcs_fwlog.c

802

pci_config_get32(pwp->pci_acc_handle, PMCS_PCI_PBA_OFFSET));

usr/src/uts/common/io/scsi/adapters/pmcs/pmcs_fwlog.c

804

pci_config_get32(pwp->pci_acc_handle, PMCS_PCI_PCIE_CAP_HD));

usr/src/uts/common/io/scsi/adapters/pmcs/pmcs_fwlog.c

806

pci_config_get32(pwp->pci_acc_handle, PMCS_PCI_UE_STAT));

usr/src/uts/common/io/scsi/adapters/pmcs/pmcs_fwlog.c

808

pci_config_get32(pwp->pci_acc_handle, PMCS_PCI_UE_MASK));

usr/src/uts/common/io/scsi/adapters/pmcs/pmcs_fwlog.c

810

pci_config_get32(pwp->pci_acc_handle, PMCS_PCI_UE_SEV));

usr/src/uts/common/io/scsi/adapters/pmcs/pmcs_fwlog.c

812

pci_config_get32(pwp->pci_acc_handle, PMCS_PCI_CE_STAT));

usr/src/uts/common/io/scsi/adapters/pmcs/pmcs_fwlog.c

814

pci_config_get32(pwp->pci_acc_handle, PMCS_PCI_CE_MASK));

usr/src/uts/common/io/scsi/adapters/pmcs/pmcs_fwlog.c

816

pci_config_get32(pwp->pci_acc_handle, PMCS_PCI_ADV_ERR_CTRL));

usr/src/uts/common/io/scsi/adapters/pmcs/pmcs_fwlog.c

819

"0x%08x\n", i, pci_config_get32(pwp->pci_acc_handle,

usr/src/uts/common/io/sfe/sfe.c

2028

iline = pci_config_get32(conf_handle, PCI_CONF_ILINE);

usr/src/uts/common/io/sfe/sfe_util.c

5276

pci_cap = pci_config_get32(conf_handle, pci_cap_ptr);

usr/src/uts/common/io/sfe/sfe_util.c

5312

pmcsr = pci_config_get32(conf_handle, pci_cap_ptr + PCI_PMCSR);

usr/src/uts/common/io/usb/hcd/ehci/ehci_util.c

1413

extended_cap = pci_config_get32(ehcip->ehci_config_handle,

usr/src/uts/common/io/usb/hcd/ehci/ehci_util.c

1486

extended_cap = pci_config_get32(

usr/src/uts/common/io/usb/hcd/xhci/xhci_quirks.c

69

ports = pci_config_get32(xhcip->xhci_cfg_handle,

usr/src/uts/common/io/usb/hcd/xhci/xhci_quirks.c

74

ports = pci_config_get32(xhcip->xhci_cfg_handle,

usr/src/uts/common/io/xge/drv/xge_osdep.h

311

(*(val) = pci_config_get32(cfgh, where))

usr/src/uts/common/io/yge/yge.c

591

val = pci_config_get32(dev->d_pcih, PCI_OUR_REG_1);

usr/src/uts/common/io/yge/yge.c

615

our = pci_config_get32(dev->d_pcih, PCI_OUR_REG_4);

usr/src/uts/common/io/yge/yge.c

622

our = pci_config_get32(dev->d_pcih, PCI_OUR_REG_5);

usr/src/uts/common/io/yge/yge.c

650

val = pci_config_get32(dev->d_pcih, PCI_OUR_REG_1);

usr/src/uts/common/io/yge/yge.c

745

val = pci_config_get32(pcih, PCI_OUR_REG_1);

usr/src/uts/common/os/pcifm.c

118

pcix_ecc_regs->pcix_ecc_ctlstat = pci_config_get32(erpt_p->pe_hdl,

usr/src/uts/common/os/pcifm.c

125

pcix_ecc_regs->pcix_ecc_fstaddr = pci_config_get32(erpt_p->pe_hdl,

usr/src/uts/common/os/pcifm.c

128

pcix_ecc_regs->pcix_ecc_secaddr = pci_config_get32(erpt_p->pe_hdl,

usr/src/uts/common/os/pcifm.c

131

pcix_ecc_regs->pcix_ecc_attr = pci_config_get32((

usr/src/uts/common/os/pcifm.c

153

pcix_bdg_regs->pcix_bdg_stat = pci_config_get32(erpt_p->pe_hdl,

usr/src/uts/common/os/pcifm.c

181

pcix_regs->pcix_status = pci_config_get32(erpt_p->pe_hdl,

usr/src/uts/common/os/sunpci.c

369

*p = pci_config_get32(confhdl, offset);

usr/src/uts/common/os/sunpci.c

421

chsp->chs_base0 = pci_config_get32(confhdl, PCI_CONF_BASE0);

usr/src/uts/common/os/sunpci.c

422

chsp->chs_base1 = pci_config_get32(confhdl, PCI_CONF_BASE1);

usr/src/uts/common/os/sunpci.c

423

chsp->chs_base2 = pci_config_get32(confhdl, PCI_CONF_BASE2);

usr/src/uts/common/os/sunpci.c

424

chsp->chs_base3 = pci_config_get32(confhdl, PCI_CONF_BASE3);

usr/src/uts/common/os/sunpci.c

425

chsp->chs_base4 = pci_config_get32(confhdl, PCI_CONF_BASE4);

usr/src/uts/common/os/sunpci.c

426

chsp->chs_base5 = pci_config_get32(confhdl, PCI_CONF_BASE5);

usr/src/uts/common/os/sunpci.c

556

*regbuf = pci_config_get32(confhdl, cap_ptr);

usr/src/uts/common/os/sunpci.c

802

(void) pci_config_get32(confhdl, PCI_CONF_BASE5);

usr/src/uts/common/sys/sunddi.h

2021

pci_config_get32(ddi_acc_handle_t handle, off_t offset);

usr/src/uts/i86pc/io/apix/apix.c

1700

msi_pvm = pci_config_get32(handle, msi_mask_off);

usr/src/uts/i86pc/io/apix/apix.c

1704

pci_config_get32(handle, msi_mask_off)));

usr/src/uts/i86pc/io/apix/apix.c

1715

pci_config_get32(handle, msi_mask_off)));

usr/src/uts/i86pc/io/pcplusmp/apic_introp.c

597

msi_pvm = pci_config_get32(handle, msi_mask_off);

usr/src/uts/i86pc/io/pcplusmp/apic_introp.c

601

pci_config_get32(handle, msi_mask_off)));

usr/src/uts/i86pc/io/pcplusmp/apic_introp.c

632

pci_config_get32(handle, msi_mask_off)));

usr/src/uts/i86pc/os/cmi_hw.c

1929

val = pci_config_get32(hdl, (off_t)reg);

usr/src/uts/intel/io/amdnbtemp/amdnbtemp.c

111

at->at_raw = pci_config_get32(at->at_cfgspace, AMDNBTEMP_TEMPREG);

usr/src/uts/intel/io/amdzen/amdzen.c

255

return (pci_config_get32(stub->azns_cfgspace, reg));

usr/src/uts/intel/io/amr/amrreg.h

638

#define AMR_QGET_IDB(sc) pci_config_get32(sc->regsmap_handle, \

usr/src/uts/intel/io/amr/amrreg.h

642

#define AMR_QGET_ODB(sc) pci_config_get32(sc->regsmap_handle, \

usr/src/uts/intel/io/dktp/controller/ata/sil3xxx.h

87

rval = pci_config_get32(handle, PCI_CONF_BA5_IND_ACCESS); \

usr/src/uts/intel/io/dnet/dnet.c

460

csr = pci_config_get32(handle, PCI_CONF_COMM);

usr/src/uts/intel/io/dnet/dnet.c

565

csr = pci_config_get32(handle, PCI_CONF_COMM);

usr/src/uts/intel/io/dnet/dnet.c

569

csr = pci_config_get32(handle, PCI_DNET_CONF_CFDD);

usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c

1935

offset, pci_config_get32(handle, offset));

usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c

1938

pci_config_get32(handle, offset + 4));

usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c

1960

offset, pci_config_get32(handle, offset));

usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c

1974

offset, pci_config_get32(handle, offset));

usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c

3599

request = pci_config_get32(config_handle, i);

usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c

3640

request = pci_config_get32(config_handle, PCI_CONF_ROM);

usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c

3681

base = pci_config_get32(config_handle, i);

usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c

3683

request = pci_config_get32(config_handle, i);

usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c

3700

base_hi = pci_config_get32(config_handle, i+4);

usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c

3738

base = pci_config_get32(config_handle, PCI_CONF_ROM);

usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c

3740

request = pci_config_get32(config_handle, PCI_CONF_ROM);

usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c

419

pci_config_get32(config_handle, PCI_CONF_BASE0));

usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c

421

pci_config_get32(config_handle, PCI_CONF_BASE1));

usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c

433

pci_config_get32(config_handle, PCI_CONF_BASE2));

usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c

435

pci_config_get32(config_handle, PCI_CONF_BASE3));

usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c

437

pci_config_get32(config_handle, PCI_CONF_BASE4));

usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c

439

pci_config_get32(config_handle, PCI_CONF_BASE5));

usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c

441

pci_config_get32(config_handle, PCI_CONF_CIS));

usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c

447

pci_config_get32(config_handle, PCI_CONF_ROM));

usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c

490

pci_config_get32(config_handle, PCI_BCNF_PF_BASE_HIGH));

usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c

492

pci_config_get32(config_handle, PCI_BCNF_PF_LIMIT_HIGH));

usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c

498

pci_config_get32(config_handle, PCI_BCNF_ROM));

usr/src/uts/intel/io/imc/imc.c

1187

mtr = pci_config_get32(chan->ich_desc->istub_cfgspace,

usr/src/uts/intel/io/imc/imc.c

1208

mcmtr = pci_config_get32(icn->icn_main0->istub_cfgspace,

usr/src/uts/intel/io/imc/imc.c

1250

icn->icn_topo = pci_config_get32(icn->icn_m2m->istub_cfgspace,

usr/src/uts/intel/io/imc/imc.c

1486

tolm = pci_config_get32(sad->isad_tolh->istub_cfgspace,

usr/src/uts/intel/io/imc/imc.c

1488

tohm_low = pci_config_get32(sad->isad_tolh->istub_cfgspace,

usr/src/uts/intel/io/imc/imc.c

1491

tohm_hi = pci_config_get32(sad->isad_tolh->istub_cfgspace,

usr/src/uts/intel/io/imc/imc.c

1698

dram = pci_config_get32(sad->isad_dram->istub_cfgspace, off);

usr/src/uts/intel/io/imc/imc.c

1699

interleave = pci_config_get32(sad->isad_dram->istub_cfgspace,

usr/src/uts/intel/io/imc/imc.c

1882

val = pci_config_get32(tad->itad_stub->istub_cfgspace, off);

usr/src/uts/intel/io/imc/imc.c

1893

val = pci_config_get32(tad->itad_stub->istub_cfgspace, baseoff);

usr/src/uts/intel/io/imc/imc.c

1924

val = pci_config_get32(tad->itad_stub->istub_cfgspace,

usr/src/uts/intel/io/imc/imc.c

1934

val = pci_config_get32(mc->icn_main1->istub_cfgspace,

usr/src/uts/intel/io/imc/imc.c

1958

val = pci_config_get32(tad->itad_stub->istub_cfgspace,

usr/src/uts/intel/io/imc/imc.c

1991

val = pci_config_get32(chan->ich_desc->istub_cfgspace,

usr/src/uts/intel/io/imc/imc.c

2071

val = pci_config_get32(chan->ich_desc->istub_cfgspace, off);

usr/src/uts/intel/io/imc/imc.c

2107

val = pci_config_get32(chan->ich_desc->istub_cfgspace, off);

usr/src/uts/intel/io/imc/imc.c

651

val = pci_config_get32(stub->istub_cfgspace,

usr/src/uts/intel/io/imc/imc.c

703

busno = pci_config_get32(stub->istub_cfgspace,

usr/src/uts/intel/io/imc/imc.c

986

nodeid = pci_config_get32(h,

usr/src/uts/intel/io/mc-amd/mcamd_pcicfg.c

84

return (pci_config_get32(hdlp->cfh_hdl, offset));

usr/src/uts/intel/io/pciex/pcieb_x86.c

500

data = (uint32_t)pci_config_get32(cfg_hdl,

usr/src/uts/intel/io/pciex/pcieb_x86.c

506

value = (uint32_t)pci_config_get32(cfg_hdl,

usr/src/uts/intel/io/pciex/pcieb_x86.c

595

pexctrl = pci_config_get32(bus_p->bus_cfg_hdl,

usr/src/uts/intel/io/scsi/adapters/arcmsr/arcmsr.c

2527

wlval = pci_config_get32(acb->pci_acc_handle, 0);

usr/src/uts/intel/io/vmm/io/ppt.c

185

cio.pci_data = pci_config_get32(cfg, cio.pci_off);

usr/src/uts/intel/io/vmm/io/ppt.c

342

off = pci_config_get32(ppt->pptd_cfg, base + PCI_MSIX_TBL_OFFSET);

usr/src/uts/sun4/io/pcicfg.c

1992

pci_config_get32(handle, offset));

usr/src/uts/sun4/io/pcicfg.c

1995

pci_config_get32(handle, offset + 4));

usr/src/uts/sun4/io/pcicfg.c

2013

pci_config_get32(handle, offset));

usr/src/uts/sun4/io/pcicfg.c

2027

pci_config_get32(handle, offset));

usr/src/uts/sun4/io/pcicfg.c

4212

request = pci_config_get32(config_handle, i);

usr/src/uts/sun4/io/pcicfg.c

4255

request = pci_config_get32(config_handle, PCI_CONF_ROM);

usr/src/uts/sun4/io/pcicfg.c

4499

request = pci_config_get32(h, PCI_CONF_ROM);

usr/src/uts/sun4/io/pcicfg.c

450

pci_config_get32(config_handle, PCI_CONF_BASE0));

usr/src/uts/sun4/io/pcicfg.c

452

pci_config_get32(config_handle, PCI_CONF_BASE1));

usr/src/uts/sun4/io/pcicfg.c

464

pci_config_get32(config_handle, PCI_CONF_BASE2));

usr/src/uts/sun4/io/pcicfg.c

466

pci_config_get32(config_handle, PCI_CONF_BASE3));

usr/src/uts/sun4/io/pcicfg.c

468

pci_config_get32(config_handle, PCI_CONF_BASE4));

usr/src/uts/sun4/io/pcicfg.c

470

pci_config_get32(config_handle, PCI_CONF_BASE5));

usr/src/uts/sun4/io/pcicfg.c

472

pci_config_get32(config_handle, PCI_CONF_CIS));

usr/src/uts/sun4/io/pcicfg.c

478

pci_config_get32(config_handle, PCI_CONF_ROM));

usr/src/uts/sun4/io/pcicfg.c

4800

base = pci_config_get32(config_handle, i);

usr/src/uts/sun4/io/pcicfg.c

4802

request = pci_config_get32(config_handle, i);

usr/src/uts/sun4/io/pcicfg.c

4819

base_hi = pci_config_get32(config_handle, i+4);

usr/src/uts/sun4/io/pcicfg.c

4859

base = pci_config_get32(config_handle, PCI_CONF_ROM);

usr/src/uts/sun4/io/pcicfg.c

4861

request = pci_config_get32(config_handle, PCI_CONF_ROM);

usr/src/uts/sun4/io/pcicfg.c

522

pci_config_get32(config_handle, PCI_BCNF_PF_BASE_HIGH));

usr/src/uts/sun4/io/pcicfg.c

524

pci_config_get32(config_handle, PCI_BCNF_PF_LIMIT_HIGH));

usr/src/uts/sun4/io/pcicfg.c

530

pci_config_get32(config_handle, PCI_BCNF_ROM));

usr/src/uts/sun4/io/pcicfg.c

6026

request = pci_config_get32(h, i);

usr/src/uts/sun4u/io/pci/db21554.c

1034

pci_config_get32(dbp->conf_handle,

usr/src/uts/sun4u/io/pci/db21554.c

1039

pci_config_get32(dbp->conf_handle,

usr/src/uts/sun4u/io/pci/db21554.c

1044

pci_config_get32(dbp->conf_handle,