outw
void outw(u_int port, u_short data);
void outw(u_int port, u_short data);
outw(RX_RESET, BASE + VX_COMMAND);
outw(TX_RESET, BASE + VX_COMMAND);
outw(SET_RD_0_MASK | S_CARD_FAILURE | S_RX_COMPLETE |
outw(SET_INTR_MASK | S_CARD_FAILURE | S_RX_COMPLETE |
outw(ACK_INTR | 0xff, BASE + VX_COMMAND);
outw(SET_RX_FILTER | FIL_INDIVIDUAL |
outw(RX_ENABLE, BASE + VX_COMMAND);
outw(TX_ENABLE, BASE + VX_COMMAND);
outw(TX_RESET, BASE + VX_COMMAND);
outw(TX_ENABLE, BASE + VX_COMMAND);
outw(len, BASE + VX_W1_TX_PIO_WR_1);
outw(0x0, BASE + VX_W1_TX_PIO_WR_1); /* Second dword meaningless */
outw(t, BASE + VX_W1_TX_PIO_WR_1);
outw(ACK_INTR | cst, BASE + VX_COMMAND);
outw(C_INTR_LATCH, BASE + VX_COMMAND);
outw(RX_DISCARD_TOP_PACK, BASE + VX_COMMAND);
outw(RX_DISCARD_TOP_PACK, BASE + VX_COMMAND);
outw(EEPROM_CMD_RD | offset, BASE + VX_W0_EEPROM_COMMAND);
outw(STOP_TRANSCEIVER, BASE + VX_COMMAND);
outw(0, BASE + VX_W4_MEDIA_TYPE);
outw(ENABLE_UTP, BASE + VX_W4_MEDIA_TYPE);
outw(START_TRANSCEIVER,BASE + VX_COMMAND);
outw(LINKBEAT_ENABLE, BASE + VX_W4_MEDIA_TYPE);
outw(STOP_TRANSCEIVER, BASE + VX_COMMAND);
outw(0, BASE + VX_W4_MEDIA_TYPE);
outw(GLOBAL_RESET, BASE + VX_COMMAND);
outw(ntohs(p[i]), BASE + VX_W2_ADDR_0 + (i * 2));
outw(RX_DISABLE, BASE + VX_COMMAND);
outw(RX_DISCARD_TOP_PACK, BASE + VX_COMMAND);
outw(TX_DISABLE, BASE + VX_COMMAND);
outw(STOP_TRANSCEIVER, BASE + VX_COMMAND);
outw(RX_RESET, BASE + VX_COMMAND);
outw(TX_RESET, BASE + VX_COMMAND);
outw(C_INTR_LATCH, BASE + VX_COMMAND);
outw(SET_RD_0_MASK, BASE + VX_COMMAND);
outw(SET_INTR_MASK, BASE + VX_COMMAND);
outw(SET_RX_FILTER, BASE + VX_COMMAND);
#define GO_WINDOW(x) outw(WINDOW_SELECT|(x),BASE+VX_COMMAND)
outw(val, ioaddr + regCommandIntStatus_w);
outw(address + ((0x02)<<6), ioaddr + regEepromCommand_0_w);
outw(0x30, ioaddr + regEepromCommand_0_w);
outw(address + ((0x03)<<6), ioaddr + regEepromCommand_0_w);
outw(value, ioaddr + regEepromData_0_w);
outw(0x30, ioaddr + regEepromCommand_0_w);
outw(address + ((0x01)<<6), ioaddr + regEepromCommand_0_w);
outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+0);
outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+2);
outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+4);
outw(cmdRxDisable, INF_3C90X.IOAddr + regCommandIntStatus_w);
outw(cmdTxDisable, INF_3C90X.IOAddr + regCommandIntStatus_w);
outw(htons(eeprom[HWADDR_OFFSET + 0]), INF_3C90X.IOAddr + regStationAddress_2_3w);
outw(htons(eeprom[HWADDR_OFFSET + 1]), INF_3C90X.IOAddr + regStationAddress_2_3w+2);
outw(htons(eeprom[HWADDR_OFFSET + 2]), INF_3C90X.IOAddr + regStationAddress_2_3w+4);
outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+0);
outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+2);
outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+4);
outw(EE_ENB, ee_addr); udelay(2);
outw(EE_ENB | EE_SHIFT_CLK, ee_addr); udelay(2);
outw(dataval, ee_addr); udelay(2);
outw(dataval | EE_SHIFT_CLK, ee_addr); udelay(2);
outw(EE_ENB, ee_addr); udelay(2);
outw(EE_ENB & ~EE_CS, ee_addr);
outw(status & 0xfc00, ioaddr + SCBStatus);
outw(INT_MASK | CU_START, ioaddr + SCBCmd);
outw(INT_MASK | RX_START, ioaddr + SCBCmd);
outw(INT_MASK, ioaddr + SCBCmd);
outw(intr_status, ioaddr + SCBStatus);
outw(INT_MASK | RX_ADDR_LOAD, ioaddr + SCBCmd);
outw(INT_MASK | CU_STATSADDR, ioaddr + SCBCmd);
outw(INT_MASK | RX_START, ioaddr + SCBCmd);
outw(INT_MASK | RX_START, ioaddr + SCBCmd);
outw(INT_MASK | CU_CMD_BASE, ioaddr + SCBCmd);
outw(INT_MASK | CU_START, ioaddr + SCBCmd);
outw(((unsigned short *)mc_filter)[i], mc0 + i*4);
outw(0x0001, ioaddr + PGSEL);
outw(0x189C, ioaddr + PMDCSR);
outw(0x0000, ioaddr + TSTDAT);
outw(0x5040, ioaddr + DSPCFG);
outw(0x008C, ioaddr + SDCFG);
outw(nic->node_addr[i] + (nic->node_addr[i+1] << 8), ioaddr + RxFilterData);
outw(*((unsigned short *)src), eth_asic_base + ASIC_PIO);
outw(value, 0xCFC + (where&2));
outw(index, addr + PCNET32_WIO_RAP);
outw(index, addr + PCNET32_WIO_RAP);
outw(val, addr + PCNET32_WIO_RDP);
outw(index, addr + PCNET32_WIO_RAP);
outw(index, addr + PCNET32_WIO_RAP);
outw(val, addr + PCNET32_WIO_BDP);
outw(val, addr + PCNET32_WIO_RAP);
outw(88, addr + PCNET32_WIO_RAP);
outw ( input_length, nic->ioaddr + PNIC_REG_LEN );
outw ( command, nic->ioaddr + PNIC_REG_CMD );
outw(0, nic->ioaddr + IntrMask);
outw(status & (TxOK | TxErr | PCIErr), nic->ioaddr + IntrStatus);
outw(status & ~(RxFIFOOver | RxOverflow | RxOK), nic->ioaddr + IntrStatus);
outw(cur_rx - 16, nic->ioaddr + RxBufPtr);
outw(status & (RxFIFOOver | RxOverflow | RxOK), nic->ioaddr + IntrStatus);
outw(mask, nic->ioaddr + IntrMask);
outw(inw(BASE + MACCtrl0) | EnbFullDuplex,
outw(inw(BASE + MACCtrl0) | duplex ? 0x20 : 0,
outw(addr16, BASE + StationAddr);
outw(addr16, BASE + StationAddr + 2);
outw(addr16, BASE + StationAddr + 4);
outw(sdc->mtu + 14, BASE + MaxFrameSize);
outw(0, BASE + DownCounter);
outw(RxEnable | TxEnable, BASE + MACCtrl1);
outw(intr_status, nic->ioaddr + IntrEnable);
outw(0x0200, BASE + ASICCtrl);
outw(intr_status, nic->ioaddr + IntrStatus);
outw(DEFAULT_INTR & ~(IntrRxDone|IntrRxDMADone),
outw(TxDisable, BASE + MACCtrl1);
outw(TxEnable, BASE + MACCtrl1);
outw(0, BASE + TxStatus);
outw(TxDisable, BASE + MACCtrl1);
outw(0x0000, BASE + IntrEnable);
outw(TxDisable | RxDisable | StatsDisable, BASE + MACCtrl1);
outw(0x007f, BASE + ASICCtrl + 2);
outw(inw(BASE + MulticastFilter1 + 2) | 0x0200,
outw(inw(BASE + MACCtrl0) | EnbFlowCtrl, BASE + MACCtrl0);
outw(0x0200 | (location & 0xff), ioaddr + EECtrl);
outw(mc_filter[i], BASE + MulticastFilter0 + i * 2);
outw(TLAN_NET_SIO, io_base + TLAN_DIO_ADR);
outw(TLAN_NET_SIO, io_base + TLAN_DIO_ADR);
outw(TLAN_NET_SIO, BASE + TLAN_DIO_ADR);
outw(TLAN_NET_SIO, base_port + TLAN_DIO_ADR);
outw(TLAN_NET_SIO, base_port + TLAN_DIO_ADR);
outw(TLAN_NET_SIO, BASE + TLAN_DIO_ADR);
outw(TLAN_NET_SIO, BASE + TLAN_DIO_ADR);
outw(host_int, BASE + TLAN_HOST_INT);
outw(data, BASE + TLAN_HOST_CMD);
outw(TLAN_NET_SIO, io_base + TLAN_DIO_ADR);
outw(internal_addr, base_addr + TLAN_DIO_ADR);
outw(internal_addr, base_addr + TLAN_DIO_ADR);
outw(internal_addr, base_addr + TLAN_DIO_ADR);
outw(internal_addr, base_addr + TLAN_DIO_ADR);
outw(internal_addr, base_addr + TLAN_DIO_ADR);
outw(data, base_addr + TLAN_DIO_DATA + (internal_addr & 0x2));
outw(internal_addr, base_addr + TLAN_DIO_ADR);
outw(0x0008, ioaddr + CSR15);
outw (CR_FDX, byCR0);
outw (0x0000, byIMR0);
outw (CR_FDX, byCR0);
outw ((CRbak | CR_STRT | CR_TXON | CR_RXON | CR_DPOLL), byCR0);
outw (IMRShadow, byIMR0);
outw(intr_status & 0xffff, nic->ioaddr + IntrStatus);
outw(DEFAULT_INTR & ~IntrRxDone, nic->ioaddr + IntrStatus);
outw (ReadMIItmp, wMIIDATA);
outw(intr_status, nic->ioaddr + IntrEnable);
outw(0x0010, nic->ioaddr + 0x84);
#define writew outw
void outw(uint16_t, uint16_t);
outw(IOP_TEST_VALUE, start);
outw(IOP_TEST_VALUE, end);
extern void outw(int port, uint16_t value);
outw(port, (uint16_t)local_data);
outw(PCI_CONFDATA | (reg & 0x2), val);
outw(PCI_CONFDATA | (reg & 0x2), val);
outw(PCI_CADDR2(device, reg), val);
outw(Address, Value);
outw((uintptr_t)addr, value);
outw((uintptr_t)addr, ddi_swap16(value));
outw(port, *h++);
outw(port, *h++);
outw(port, ddi_swap16(*h++));
outw(port, ddi_swap16(*h++));
outw((uintptr_t)addr, ddi_swap16(value));
outw(port, ddi_swap16(*h++));
outw(port, ddi_swap16(*h++));
extern void outw(int port, uint16_t value);