ohci_regs
&soft_state->ohci->ohci_regs->link_ctrl_clr,
&soft_state->ohci->ohci_regs->link_ctrl_clr, 0xFFFFFFFF);
&soft_state->ohci->ohci_regs->link_ctrl_clr,
&soft_statep->ohci->ohci_regs->it[i];
&soft_statep->ohci->ohci_regs->ir[i];
&ohci_hdl->ohci_regs->phy_ctrl);
ddi_put32(ohci_hdl->ohci_reg_handle, &ohci_hdl->ohci_regs->phy_ctrl,
(caddr_t *)&ohci->ohci_regs, 0, 0, &drvinfo->di_reg_attr,
&ohci_hdl->ohci_regs->phy_ctrl);
&ohci_hdl->ohci_regs->intr_event_clr,
&ohci_hdl->ohci_regs->phy_ctrl) & OHCI_PHYC_RDDATA_MASK) >>
&ohci_hdl->ohci_regs->phy_ctrl);
&ohci_hdl->ohci_regs->phy_ctrl, ohci_reg);
&ohci_hdl->ohci_regs->phy_ctrl);
&ohci_hdl->ohci_regs->node_id);
&ohci_hdl->ohci_regs->self_id_count);
&ohci_hdl->ohci_regs->posted_write_addrhi);
&ohci_hdl->ohci_regs->posted_write_addrlo);
&ohci_hdl->ohci_regs->guid_hi);
&ohci_hdl->ohci_regs->guid_lo);
&ohci_hdl->ohci_regs->csr_data, swap);
&ohci_hdl->ohci_regs->csr_compare_data, compare);
&ohci_hdl->ohci_regs->csr_ctrl, offset & OHCI_CSR_SELECT);
&ohci_hdl->ohci_regs->csr_ctrl);
&ohci_hdl->ohci_regs->csr_data);
&ohci_hdl->ohci_regs->phys_req_filterhi_set, data);
&ohci_hdl->ohci_regs->phys_req_filterlo_set, data);
&ohci_hdl->ohci_regs->phys_req_filterhi_clr, data);
&ohci_hdl->ohci_regs->phys_req_filterlo_clr, data);
&ohci_hdl->ohci_regs->config_rom_hdr, 0);
ddi_get32(ohci->ohci_reg_handle, &ohci->ohci_regs->vendor_id);
&ohci_hdl->ohci_regs->bus_options, OHCI_SWAP32(data[2]));
version = ddi_get32(ohci->ohci_reg_handle, &ohci->ohci_regs->version);
&ohci_hdl->ohci_regs->config_rom_hdr, OHCI_SWAP32(data[0]));
&ohci_hdl->ohci_regs->node_id);
&ohci_hdl->ohci_regs->node_id, reg);
&ohci_hdl->ohci_regs->node_id);
&ohci_hdl->ohci_regs->isoch_cycle_timer);
&ohci_hdl->ohci_regs->isoch_cycle_timer, cycle_time);
&ohci_hdl->ohci_regs->isoch_cycle_timer);
&ohci_hdl->ohci_regs->at_retries);
&ohci_hdl->ohci_regs->at_retries);
&ohci_hdl->ohci_regs->at_retries, reg);
&ohci_hdl->ohci_regs->isoch_cycle_timer);
&ohci_hdl->ohci_regs->node_id);
&ohci_hdl->ohci_regs->bus_options);
&ohci_hdl->ohci_regs->intr_event_clr, OHCI_INTR_CYC_TOO_LONG);
&ohci_hdl->ohci_regs->link_ctrl_set, OHCI_LC_CYC_MAST);
&ohci_hdl->ohci_regs->link_ctrl_clr, OHCI_LC_CYC_MAST);
&ohci_hdl->ohci_regs->config_rom_maplo,
&ohci_hdl->ohci_regs->self_id_buflo,
&ohci_hdl->ohci_regs->bus_options, OHCI_SWAP32(quadlet));
&ohci_hdl->ohci_regs->config_rom_hdr, OHCI_SWAP32(quadlet));
&ohci_hdl->ohci_regs->self_id_buflo,
&ohci_hdl->ohci_regs->link_ctrl_set, OHCI_LC_RCV_SELF);
&ohci_hdl->ohci_regs->self_id_count);
&ohci_hdl->ohci_regs->config_rom_maplo,
&ohci_hdl->ohci_regs->bus_options) | (OHCI_BOPT_IRMC |
&ohci_hdl->ohci_regs->at_req.ctxt_ctrl_set);
&ohci_hdl->ohci_regs->at_resp.ctxt_ctrl_set);
&ohci_hdl->ohci_regs->at_req.cmd_ptrlo, cmdptr);
&ohci_hdl->ohci_regs->at_req.ctxt_ctrl_set, OHCI_CC_RUN_MASK);
&ohci_hdl->ohci_regs->at_req.ctxt_ctrl_set, OHCI_CC_WAKE_MASK);
&ohci_hdl->ohci_regs->at_req.ctxt_ctrl_clr, OHCI_CC_RUN_MASK);
&ohci_hdl->ohci_regs->ar_resp.cmd_ptrlo, cmdptr);
&ohci_hdl->ohci_regs->ar_resp.ctxt_ctrl_set, OHCI_CC_RUN_MASK);
&ohci_hdl->ohci_regs->ar_resp.ctxt_ctrl_set, OHCI_CC_WAKE_MASK);
&ohci_hdl->ohci_regs->ar_resp.ctxt_ctrl_clr, OHCI_CC_RUN_MASK);
&ohci_hdl->ohci_regs->ar_req.cmd_ptrlo, cmdptr);
&ohci_hdl->ohci_regs->ar_req.ctxt_ctrl_set, OHCI_CC_RUN_MASK);
&ohci_hdl->ohci_regs->ar_req.ctxt_ctrl_set, OHCI_CC_WAKE_MASK);
&ohci_hdl->ohci_regs->ar_req.ctxt_ctrl_clr, OHCI_CC_RUN_MASK);
&ohci_hdl->ohci_regs->at_resp.cmd_ptrlo, cmdptr);
&ohci_hdl->ohci_regs->at_resp.ctxt_ctrl_set, OHCI_CC_RUN_MASK);
&ohci_hdl->ohci_regs->at_resp.ctxt_ctrl_set, OHCI_CC_WAKE_MASK);
&ohci_hdl->ohci_regs->at_resp.ctxt_ctrl_clr, OHCI_CC_RUN_MASK);
&ohci_hdl->ohci_regs->hc_ctrl_set);
&ohci_hdl->ohci_regs->hc_ctrl_set, OHCI_HC_APHY_ENBL);
&ohci_hdl->ohci_regs->hc_ctrl_set);
&ohci_hdl->ohci_regs->hc_ctrl_set, OHCI_HC_APHY_ENBL);
&ohci_hdl->ohci_regs->hc_ctrl_clr, OHCI_HC_NO_BSWAP |
&ohci_hdl->ohci_regs->hc_ctrl_set, OHCI_HC_NO_BSWAP |
&ohci_hdl->ohci_regs->hc_ctrl_set, OHCI_HC_LPS |
&ohci_hdl->ohci_regs->ir_multi_maskhi_clr, 0xFFFFFFFF);
&ohci_hdl->ohci_regs->ir_multi_masklo_clr, 0xFFFFFFFF);
&ohci_hdl->ohci_regs->at_retries, 0x00000002);
&ohci_hdl->ohci_regs->link_ctrl_clr, 0xFFFFFFFF);
&ohci_hdl->ohci_regs->link_ctrl_set, OHCI_LC_CYC_MAST |
&ohci_hdl->ohci_regs->phys_upper_bound, (uint32_t)0x0000FFFF);
&ohci_hdl->ohci_regs->ar_req_filterhi_set, (uint32_t)0x80000000);
&ohci_hdl->ohci_regs->it_intr_event_clr, (uint32_t)0xFFFFFFFF);
&ohci_hdl->ohci_regs->it_intr_mask_clr, (uint32_t)0xFFFFFFFF);
&ohci_hdl->ohci_regs->ir_intr_event_clr, (uint32_t)0xFFFFFFFF);
&ohci_hdl->ohci_regs->ir_intr_mask_clr, (uint32_t)0xFFFFFFFF);
&ohci_hdl->ohci_regs->intr_event_clr, (uint32_t)0xFFFFFFFF);
&ohci_hdl->ohci_regs->intr_mask_clr, (uint32_t)0xFFFFFFFF);
&ohci_hdl->ohci_regs->hc_ctrl_set, OHCI_HC_SOFT_RESET);
&ohci_hdl->ohci_regs->hc_ctrl_set);
addr = (uint32_t *)((uintptr_t)ohci_hdl->ohci_regs +
addr = (uint32_t *)((uintptr_t)ohci_hdl->ohci_regs +
&ohci_hdl->ohci_regs->intr_mask_set, OHCI_INTR_MASTER_INTR_ENBL);
&ohci_hdl->ohci_regs->intr_mask_clr, OHCI_INTR_MASTER_INTR_ENBL);
&ohci_hdl->ohci_regs->intr_event_clr);
&ohci_hdl->ohci_regs->intr_mask_set, interrupt_mask);
&ohci_hdl->ohci_regs->intr_mask_clr, interrupt_mask);
&ohci_hdl->ohci_regs->intr_event_clr, interrupt_mask);
&ohci_hdl->ohci_regs->it_intr_event_clr);
&ohci_hdl->ohci_regs->it_intr_mask_set, interrupt_mask);
&ohci_hdl->ohci_regs->it_intr_mask_clr, interrupt_mask);
&ohci_hdl->ohci_regs->it_intr_event_clr, interrupt_mask);
&ohci_hdl->ohci_regs->it_intr_mask_set, 0xFFFFFFFF);
&ohci_hdl->ohci_regs->it_intr_mask_set);
&ohci_hdl->ohci_regs->it[context_number].cmd_ptrlo,
&ohci_hdl->ohci_regs->ir_intr_event_clr);
&ohci_hdl->ohci_regs->ir_intr_mask_set, interrupt_mask);
&ohci_hdl->ohci_regs->ir_intr_mask_clr, interrupt_mask);
&ohci_hdl->ohci_regs->ir_intr_event_clr, interrupt_mask);
&ohci_hdl->ohci_regs->ir_intr_mask_set, 0xFFFFFFFF);
&ohci_hdl->ohci_regs->ir_intr_mask_set);
&ohci_hdl->ohci_regs->ir[context_number].cmd_ptrlo,
&ohci_hdl->ohci_regs->hc_ctrl_set, OHCI_HC_LINK_ENBL);
&ohci_hdl->ohci_regs->hc_ctrl_clr, OHCI_HC_LINK_ENBL);
&vendor->ve_ohci->ohci_regs->guid_hi,
&vendor->ve_ohci->ohci_regs->guid_lo,
&(HCIP)->ohci->ohci_regs->ir[(I)].ctxt_ctrl_set, \
&(HCIP)->ohci->ohci_regs->ir[(I)].ctxt_ctrl_clr, \
&(HCIP)->ohci->ohci_regs->it[(I)].ctxt_ctrl_set, 0 | \
&(HCIP)->ohci->ohci_regs->it[(I)].ctxt_ctrl_clr, 0 | \
&(HCIP)->ohci->ohci_regs->ir[(I)].ctxt_match, 0 | \
hci1394_regs_t *ohci_regs;