usr/src/uts/sun4u/io/pci/db21554.c

167

static int8_t p_latency_timer = DEF_INVALID_REG_VAL;

usr/src/uts/sun4u/io/pci/db21554.c

178

static int8_t p_cache_line_size = DEF_INVALID_REG_VAL;

usr/src/uts/sun4u/io/pci/db21554.c

193

static int8_t p_pwrite_threshold = DEF_INVALID_REG_VAL;

usr/src/uts/sun4u/io/pci/db21554.c

200

static int8_t s_pwrite_threshold = DEF_INVALID_REG_VAL;

usr/src/uts/sun4u/io/pci/db21554.c

212

static int8_t p_dread_threshold = DEF_INVALID_REG_VAL;

usr/src/uts/sun4u/io/pci/db21554.c

224

static int8_t s_dread_threshold = DEF_INVALID_REG_VAL;

usr/src/uts/sun4u/io/pci/db21554.c

233

static int8_t delayed_trans_order = DEF_INVALID_REG_VAL;

usr/src/uts/sun4u/io/pci/db21554.c

797

if ((dbp->p_latency_timer != (int8_t)DEF_INVALID_REG_VAL) &&

usr/src/uts/sun4u/io/pci/db21554.c

802

if ((dbp->s_latency_timer != (int8_t)DEF_INVALID_REG_VAL) &&

usr/src/uts/sun4u/io/pci/db21554.c

807

if ((dbp->p_cache_line_size != (int8_t)DEF_INVALID_REG_VAL) &&

usr/src/uts/sun4u/io/pci/db21554.c

812

if ((dbp->s_cache_line_size != (int8_t)DEF_INVALID_REG_VAL) &&

usr/src/uts/sun4u/io/pci/db21554.c

817

if ((dbp->p_pwrite_threshold != (int8_t)DEF_INVALID_REG_VAL) &&

usr/src/uts/sun4u/io/pci/db21554.c

825

if ((dbp->s_pwrite_threshold != (int8_t)DEF_INVALID_REG_VAL) &&

usr/src/uts/sun4u/io/pci/db21554.c

834

if ((dbp->p_dread_threshold != (int8_t)DEF_INVALID_REG_VAL) &&

usr/src/uts/sun4u/io/pci/db21554.c

844

if ((dbp->s_dread_threshold != (int8_t)DEF_INVALID_REG_VAL) &&

usr/src/uts/sun4u/io/pci/db21554.c

853

if ((dbp->delayed_trans_order != (int8_t)DEF_INVALID_REG_VAL) &&