usr/src/cmd/rmt/rmt.c
284
DEBUG1("rmtd: %c\n", key);
usr/src/cmd/rmt/rmt.c
300
DEBUG1("rmtd: s%c\n", key);
usr/src/cmd/rmt/rmt.c
359
DEBUG1("rmtd: W %s\n", count);
usr/src/cmd/rmt/rmt.c
366
DEBUG1(gettext("%s: premature eof\n"),
usr/src/cmd/rmt/rmt.c
384
DEBUG1("rmtd: R %s\n", count);
usr/src/cmd/rmt/rmt.c
419
DEBUG1("rmtd: C %s\n", device);
usr/src/cmd/rmt/rmt.c
473
DEBUG1("rmtd: A %lld\n", rval);
usr/src/uts/common/io/hotplug/hpcsvc/hpcsvc.c
454
DEBUG1("hpc_slot_register: %s", bus);
usr/src/uts/common/io/hotplug/hpcsvc/hpcsvc.c
471
DEBUG1("hpc_slot_register: %s not in bus list", bus);
usr/src/uts/common/io/hotplug/hpcsvc/hpcsvc.c
597
DEBUG1("hpc_slot_unregister: callback returned %x", r);
usr/src/uts/common/io/hotplug/hpcsvc/hpcsvc.c
607
DEBUG1("hpc_slot_unregister: freeing slot, bus_slot_list=%x",
usr/src/uts/common/io/hotplug/hpcsvc/hpcsvc.c
696
DEBUG1("hpc_remove_event_handler: handle=%x", handle);
usr/src/uts/common/io/hotplug/hpcsvc/hpcsvc.c
852
DEBUG1("hpc_slot_event_dispatcher: busp=%x", busp);
usr/src/uts/common/io/kb8042/kb8042.c
1043
#ifdef DEBUG1
usr/src/uts/common/io/ldterm.c
1203
DEBUG1(("M_STARTI down\n"));
usr/src/uts/common/io/ldterm.c
1220
DEBUG1(("M_STARTI down\n"));
usr/src/uts/common/io/ldterm.c
1472
DEBUG1(("M_STOPI down\n"));
usr/src/uts/common/io/ldterm.c
3109
DEBUG1(("ldtermwmsg:M_READ RECEIVED\n"));
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
1011
DEBUG1("pcicfg: now unloading the ntbridge driver. rc1=%d\n", rc1);
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
1144
DEBUG1("Configuring children for %p\n", dip);
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
1416
DEBUG1("ntbridge child: no \"%s\" property\n",
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
1437
DEBUG1("Failed to get assigned-addresses property %llx\n", dip);
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
1440
DEBUG1("pcicfg: ntbridge child range: dip = %s\n",
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
1775
DEBUG1("bridge assign: assigning addresses to %s\n", ddi_get_name(dip));
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
2023
DEBUG1("%llx now under configuration\n", dip);
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
2217
DEBUG1("%llx now under configuration\n", dip);
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
2417
DEBUG1("return hole at %llx\n", actual_hole_start);
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
2548
DEBUG1("ADDING 32 --->0x%x\n",
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
2555
DEBUG1("ADDING 32 --->0x%x\n",
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
2567
DEBUG1("ADDING 64 --->0x%x\n",
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
2574
DEBUG1("ADDING 64 --->0x%x\n",
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
2584
DEBUG1("ADDING I/O --->0x%x\n",
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
3032
DEBUG1("Updating ranges property for %d entries",
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
3343
DEBUG1("DOWN ROUNDED ===>[0x%x]\n",
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
3357
DEBUG1("Added [0x%x]at the top of the bridge (mem)\n", length);
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
3364
DEBUG1("DOWN ROUNDED ===>[0x%x]\n",
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
3375
DEBUG1("Added [0x%x]at the top of the bridge (PF mem)\n",
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
3398
DEBUG1("Added [0x%x]at the top of the bridge (I/O)\n", length);
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
3613
DEBUG1("BASE register [0x%x] asks for "
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
3713
DEBUG1("BASE register [0x%x] asks for [0x0]=[0x0]"
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
3887
DEBUG1("NEW bus found ->[%d]\n", new_bus);
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
4572
DEBUG1("End of bridge probe: bus_range[0] = %d\n", bus_range[0]);
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
4573
DEBUG1("End of bridge probe: bus_range[1] = %d\n", bus_range[1]);
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
4783
DEBUG1("NO DEVICEFOUND, read %x\n", tmp);
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
4790
DEBUG1("DEVICEFOUND, read %x\n", tmp);
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
4874
DEBUG1("device port_type = %x\n", port_type);
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
727
DEBUG1("Next Function - %x\n", func);
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
865
DEBUG1("ntbridge bus range start ->[%d]\n", next_bus);
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
962
DEBUG1("ntbridge: finish probing 2nd bus, rc=%d\n", rc);
usr/src/uts/sun/io/dada/conf/dcd_confsubr.c
115
#ifdef DEBUG1
usr/src/uts/sun/io/dada/conf/dcd_confsubr.c
163
#ifdef DEBUG1
usr/src/uts/sun/io/dada/conf/dcd_confsubr.c
180
#ifdef DEBUG1
usr/src/uts/sun/io/dada/conf/dcd_confsubr.c
246
#ifdef DEBUG1
usr/src/uts/sun/io/dada/conf/dcd_confsubr.c
263
#ifdef DEBUG1
usr/src/uts/sun/io/dada/conf/dcd_confsubr.c
291
#ifdef DEBUG1
usr/src/uts/sun/io/dada/impl/dcd_hba.c
193
#ifdef DEBUG1
usr/src/uts/sun/io/dada/impl/dcd_hba.c
389
#ifdef DEBUG1
usr/src/uts/sun4/io/pcicfg.c
1063
DEBUG1("ntbridge: finish probing 2nd bus, rc=%d\n", rc);
usr/src/uts/sun4/io/pcicfg.c
1118
DEBUG1("pcicfg: now unloading the ntbridge driver. rc1=%d\n", rc1);
usr/src/uts/sun4/io/pcicfg.c
1241
DEBUG1("Configuring children for %llx\n", dip);
usr/src/uts/sun4/io/pcicfg.c
1389
DEBUG1("cannot destroy ntbridge memory map size=%x\n",
usr/src/uts/sun4/io/pcicfg.c
1395
DEBUG1("cannot destroy ntbridge io map size=%x\n",
usr/src/uts/sun4/io/pcicfg.c
1485
DEBUG1("pci conf map = %d", rc);
usr/src/uts/sun4/io/pcicfg.c
1505
DEBUG1("Failed to get assigned-addresses property %llx\n", dip);
usr/src/uts/sun4/io/pcicfg.c
1508
DEBUG1("pcicfg: ntbridge child range: dip = %s\n",
usr/src/uts/sun4/io/pcicfg.c
1880
DEBUG1("bridge assign: assigning addresses to %s\n", ddi_get_name(dip));
usr/src/uts/sun4/io/pcicfg.c
2079
DEBUG1("%llx now under configuration\n", dip);
usr/src/uts/sun4/io/pcicfg.c
2252
DEBUG1("%llx now under configuration\n", dip);
usr/src/uts/sun4/io/pcicfg.c
2405
DEBUG1("Connector requires [0x%x] bytes of memory space\n",
usr/src/uts/sun4/io/pcicfg.c
2407
DEBUG1("Connector requires [0x%x] bytes of I/O space\n",
usr/src/uts/sun4/io/pcicfg.c
2543
DEBUG1("return hole at %llx\n", actual_hole_start);
usr/src/uts/sun4/io/pcicfg.c
2653
DEBUG1("ADDING 32 --->0x%x\n",
usr/src/uts/sun4/io/pcicfg.c
2662
DEBUG1("ADDING 64 --->0x%x\n",
usr/src/uts/sun4/io/pcicfg.c
2671
DEBUG1("ADDING I/O --->0x%x\n",
usr/src/uts/sun4/io/pcicfg.c
2940
DEBUG1("pcicfg_free_device_resources - Trouble freeing "
usr/src/uts/sun4/io/pcicfg.c
3762
DEBUG1("pcicfg_set_childnode_props - creating name=%s\n", name);
usr/src/uts/sun4/io/pcicfg.c
3901
DEBUG1("DOWN ROUNDED ===>[0x%x]\n",
usr/src/uts/sun4/io/pcicfg.c
3917
DEBUG1("Added [0x%x]at the top of "
usr/src/uts/sun4/io/pcicfg.c
3942
DEBUG1("Added [0x%x]at the top of "
usr/src/uts/sun4/io/pcicfg.c
4100
DEBUG1("---Vendor ID = [0x%x]\n",
usr/src/uts/sun4/io/pcicfg.c
4102
DEBUG1("---Device ID = [0x%x]\n",
usr/src/uts/sun4/io/pcicfg.c
4226
DEBUG1("BASE register [0x%x] asks for "
usr/src/uts/sun4/io/pcicfg.c
4567
DEBUG1("config_address=%x\n", po.config_address);
usr/src/uts/sun4/io/pcicfg.c
4589
DEBUG1("returned from fcode_interpreter() - "
usr/src/uts/sun4/io/pcicfg.c
4594
DEBUG1("fcode size = %x\n", fcode_size);
usr/src/uts/sun4/io/pcicfg.c
4832
DEBUG1("BASE register [0x%x] asks for "
usr/src/uts/sun4/io/pcicfg.c
4978
DEBUG1("NEW bus found ->[%d]\n", new_bus);
usr/src/uts/sun4/io/pcicfg.c
5536
DEBUG1("End of bridge probe: bus_range[0] = %d\n", bus_range[0]);
usr/src/uts/sun4/io/pcicfg.c
5537
DEBUG1("End of bridge probe: bus_range[1] = %d\n", bus_range[1]);
usr/src/uts/sun4/io/pcicfg.c
5686
DEBUG1("NO DEVICEFOUND, read %x\n", tmp);
usr/src/uts/sun4/io/pcicfg.c
5694
DEBUG1("DEVICEFOUND, read %x\n", tmp);
usr/src/uts/sun4/io/pcicfg.c
5830
DEBUG1("Can Not map in ROM %x\n", p.pci_phys_low);
usr/src/uts/sun4/io/pcicfg.c
5839
DEBUG1("Expansion ROM maps to %lx\n", addr);
usr/src/uts/sun4/io/pcicfg.c
5871
DEBUG1("Invalid ROM Signature %x\n", (uint16_t)rom_sig);
usr/src/uts/sun4/io/pcicfg.c
5934
DEBUG1("ROM is of Unknown Type 0x%x\n", code_type);
usr/src/uts/sun4/io/pcicfg.c
5978
DEBUG1("Fcode Size %x\n", *fcode_size);
usr/src/uts/sun4/io/pcicfg.c
5991
DEBUG1("Fcode Addr %lx\n", *fcode_addr);
usr/src/uts/sun4/io/pcicfg.c
6019
DEBUG1("pcicfg_fcode_assign_bars :%s\n", DEVI(dip)->devi_name);
usr/src/uts/sun4/io/pcicfg.c
6031
DEBUG1("pcicfg_fcode_assign_bars :"
usr/src/uts/sun4/io/pcicfg.c
6226
DEBUG1("assigned-addresses property len=%x\n", acount);
usr/src/uts/sun4/io/pcicfg.c
6242
DEBUG1("pcicfg_alloc_new_resources "
usr/src/uts/sun4/io/pcicfg.c
6323
DEBUG1("pcicfg_alloc_new_resources : creating 0x%x\n",
usr/src/uts/sun4/io/pcicfg.c
6379
DEBUG1("pcicfg_alloc_resource - MATCH %x\n",
usr/src/uts/sun4/io/pcicfg.c
6543
DEBUG1("updating assigned-addresss for %x\n", phys_spec.pci_phys_hi);
usr/src/uts/sun4/io/pcicfg.c
6651
DEBUG1("updating assigned-addresss for %x\n", phys_spec.pci_phys_hi);
usr/src/uts/sun4/io/pcicfg.c
6696
DEBUG1("pcicfg_remove_assigned_prop: 0x%x not removed\n",
usr/src/uts/sun4/io/pcicfg.c
680
DEBUG1("device port_type = %x\n", port_type);
usr/src/uts/sun4/io/pcicfg.c
841
DEBUG1("Next Function - %x\n", func);
usr/src/uts/sun4/io/pcicfg.c
956
DEBUG1("ntbridge bus range start ->[%d]\n", next_bus);
usr/src/uts/sun4u/io/pci/pci.c
507
DEBUG1(DBG_MAP | DBG_CONT, dip, " r#=%x", r_no);
usr/src/uts/sun4u/io/pci/pci.c
658
DEBUG1(DBG_DMA_ALLOCH, dip, "mp=%p\n", mp);
usr/src/uts/sun4u/io/pci/pci.c
838
DEBUG1(DBG_DMA_WIN, dip, "%x out of range\n", win);
usr/src/uts/sun4u/io/pci/pci_dma.c
1259
DEBUG1(DBG_BYPASS, mp->dmai_rdip, "pg0 adjust %lx\n", pg_offset);
usr/src/uts/sun4u/io/pci/pci_dma.c
1268
DEBUG1(DBG_BYPASS, mp->dmai_rdip, "last pg adjust %lx\n", pg_offset);
usr/src/uts/sun4u/io/pci/pci_dma.c
1271
DEBUG1(DBG_BYPASS, mp->dmai_rdip, "win off %p\n", win_offset);
usr/src/uts/sun4u/io/pci/pci_dma.c
668
DEBUG1(DBG_DMA_MAP|DBG_CONT, dip, "%x ", pfn);
usr/src/uts/sun4u/io/pci/pci_dma.c
676
DEBUG1(DBG_DMA_MAP, dip, "pp=%p pfns=", pp);
usr/src/uts/sun4u/io/pci/pci_dma.c
681
DEBUG1(DBG_DMA_MAP|DBG_CONT, dip, "%x ", pfn);
usr/src/uts/sun4u/io/pci/pci_dma.c
77
DEBUG1(DBG_SC|DBG_CONT, dip, " %x", dvma_addr);
usr/src/uts/sun4u/io/pci/pci_dma.c
948
DEBUG1(DBG_DMA_MAP, dip, "fast: ctx=0x%x\n", ctx);
usr/src/uts/sun4u/io/pci/pci_ecc.c
90
DEBUG1(DBG_ATTACH, dip, "ecc_create: csr=%x\n", ecc_p->ecc_csr_pa);
usr/src/uts/sun4u/io/pci/pci_ib.c
104
DEBUG1(DBG_ATTACH, dip, "ib_create: numproxy=%x\n",
usr/src/uts/sun4u/io/pci/pci_ib.c
880
DEBUG1(DBG_IB, dip, "ib_get_intr_target: ino %x\n", ino);
usr/src/uts/sun4u/io/pci/pci_ib.c
887
DEBUG1(DBG_IB, dip, "ib_get_intr_target: cpu_id %x\n", *cpu_id_p);
usr/src/uts/sun4u/io/pci/pci_ib.c
919
DEBUG1(DBG_IB, dip, "ib_set_intr_target: orig mapreg value: 0x%llx\n",
usr/src/uts/sun4u/io/pci/pci_ib.c
951
DEBUG1(DBG_IB, dip,
usr/src/uts/sun4u/io/pci/pci_ib.c
964
DEBUG1(DBG_IB, dip, "Writing new mapreg value:0x%llx\n",
usr/src/uts/sun4u/io/pci/pci_intr.c
471
DEBUG1(DBG_A_INTX, dip, "ino %x is invalid\n", ino);
usr/src/uts/sun4u/io/pci/pci_intr.c
521
DEBUG1(DBG_A_INTX, dip, "dup intr #%d\n",
usr/src/uts/sun4u/io/pci/pci_intr.c
651
DEBUG1(DBG_R_INTX, dip,
usr/src/uts/sun4u/io/pci/pci_intr.c
674
DEBUG1(DBG_R_INTX, dip, "can't get mondo for ino %x\n", ino);
usr/src/uts/sun4u/io/pci/pci_intr.c
712
DEBUG1(DBG_R_INTX, dip, "success! mondo=%x\n", mondo);
usr/src/uts/sun4u/io/pci/pci_iommu.c
125
DEBUG1(DBG_ATTACH, dip, "iommu_create: allocated size=%x\n",
usr/src/uts/sun4u/io/pci/pci_iommu.c
302
DEBUG1(DBG_MAP_WIN, dip, "iommu_map_pages: redzone pg=%x\n",
usr/src/uts/sun4u/io/pci/pci_iommu.c
350
DEBUG1(DBG_UNMAP_WIN|DBG_CONT, 0, " %x", dvma_pg);
usr/src/uts/sun4u/io/pci/pci_iommu.c
395
DEBUG1(DBG_UNMAP_WIN|DBG_CONT, dip, " %x", pg_index);
usr/src/uts/sun4u/io/pci/pci_iommu.c
398
DEBUG1(DBG_UNMAP_WIN|DBG_CONT, dip, " (context %x)", ctx);
usr/src/uts/sun4u/io/pci/pci_pbm.c
117
DEBUG1(DBG_ATTACH, dip, "pbm_create: conf=%x\n",
usr/src/uts/sun4u/io/pci/pci_pci.c
1294
DEBUG1(DBG_PWR, dip, "ppb_pwr(): ENTER level = %d\n", lvl);
usr/src/uts/sun4u/io/pci/pci_pci.c
1433
DEBUG1(DBG_PWR, dip, "ppb_set_pwr: set PM state to %s\n\n", str);
usr/src/uts/sun4u/io/pci/pci_pci.c
471
DEBUG1(DBG_ATTACH, devi,
usr/src/uts/sun4u/io/pci/pci_pci.c
984
DEBUG1(DBG_INIT_CLD, child, "Turning on XMITS NCPQ "
usr/src/uts/sun4u/io/pci/pci_pwr.c
287
DEBUG1(DBG_PWR, pwr_p->pwr_dip, "new_lvl: "
usr/src/uts/sun4u/io/pci/pci_pwr.c
298
DEBUG1(DBG_PWR, pwr_p->pwr_dip, "new_lvl: unknown "
usr/src/uts/sun4u/io/pci/pci_pwr.c
310
DEBUG1(DBG_PWR, pwr_p->pwr_dip,
usr/src/uts/sun4u/io/pci/pci_pwr.c
315
DEBUG1(DBG_PWR, pwr_p->pwr_dip,
usr/src/uts/sun4u/io/pci/pci_pwr.c
320
DEBUG1(DBG_PWR, pwr_p->pwr_dip,
usr/src/uts/sun4u/io/pci/pci_pwr.c
325
DEBUG1(DBG_PWR, pwr_p->pwr_dip,
usr/src/uts/sun4u/io/pci/pci_pwr.c
364
DEBUG1(DBG_PWR, pwr_p->pwr_dip,
usr/src/uts/sun4u/io/pci/pci_pwr.c
464
DEBUG1(DBG_PWR, pwr_p->pwr_dip,
usr/src/uts/sun4u/io/pci/pci_pwr.c
504
DEBUG1(DBG_PWR, pwr_p->pwr_dip,
usr/src/uts/sun4u/io/pci/pci_sc.c
173
DEBUG1(DBG_ATTACH, dip,
usr/src/uts/sun4u/io/pci/pci_tools.c
757
DEBUG1(DBG_TOOLS, dip, "bar returned is 0x%llx\n", *bar);
usr/src/uts/sun4u/io/pci/pci_tools.c
827
DEBUG1(DBG_TOOLS, dip, "config access: data:0x%llx\n", prg->data);
usr/src/uts/sun4u/io/pci/pci_tools.c
919
DEBUG1(DBG_TOOLS, dip,
usr/src/uts/sun4u/io/pci/pci_util.c
115
DEBUG1(DBG_ATTACH, dip, "get_pci_properties: numproxy=%d\n",
usr/src/uts/sun4u/io/pci/pci_util.c
121
DEBUG1(DBG_ATTACH, dip, "get_pci_properties: thermal_interrupt=%d\n",
usr/src/uts/sun4u/io/pci/pcipsy.c
1003
DEBUG1(DBG_ATTACH, dip,
usr/src/uts/sun4u/io/pci/pcipsy.c
532
DEBUG1(DBG_IB, dip, "pci_xlate_intr: done ino=%x\n", intr);
usr/src/uts/sun4u/io/pci/pcipsy.c
759
DEBUG1(DBG_R_INTX, dip, "remove xintr %x\n", ino);
usr/src/uts/sun4u/io/pci/pcipsy.c
891
DEBUG1(DBG_ATTACH, dip, "pbm_configure: conf status reg=%x\n", s);
usr/src/uts/sun4u/io/pci/pcipsy.c
893
DEBUG1(DBG_ATTACH, dip, "pbm_configure: conf status reg==%x\n",
usr/src/uts/sun4u/io/pci/pcipsy.c
897
DEBUG1(DBG_ATTACH, dip, "pbm_configure: ctrl reg==%llx\n", l);
usr/src/uts/sun4u/io/pci/pcipsy.c
913
DEBUG1(DBG_ATTACH, dip, "pbm_configure: %d mhz\n",
usr/src/uts/sun4u/io/pci/pcipsy.c
961
DEBUG1(DBG_ATTACH, dip, "pbm_configure: ctrl reg=%llx\n", l);
usr/src/uts/sun4u/io/pci/pcipsy.c
969
DEBUG1(DBG_ATTACH, dip, "pbm_configure: PCI diag reg==%llx\n", l);
usr/src/uts/sun4u/io/pci/pcipsy.c
982
DEBUG1(DBG_ATTACH, dip, "pbm_configure: PCI diag reg=%llx\n", l);
usr/src/uts/sun4u/io/pci/pcipsy.c
990
DEBUG1(DBG_ATTACH, dip, "pbm_configure: conf command reg=%x\n", s);
usr/src/uts/sun4u/io/pci/pcipsy.c
992
DEBUG1(DBG_ATTACH, dip, "pbm_configure: conf command reg==%x\n",
usr/src/uts/sun4u/io/pci/pcisch.c
1054
DEBUG1(DBG_DMA_MAP, iommu_p->iommu_pci_p->pci_dip,
usr/src/uts/sun4u/io/pci/pcisch.c
1075
DEBUG1(DBG_SC, dip, "ctx=%x no match\n", ctx);
usr/src/uts/sun4u/io/pci/pcisch.c
1108
DEBUG1(DBG_ATTACH, dip, "cb_create: chip id %d\n", chip_id);
usr/src/uts/sun4u/io/pci/pcisch.c
2451
DEBUG1(DBG_ERR_INTR, dip, "pci_pbm_err_handler: "
usr/src/uts/sun4u/io/pci/pcisch.c
2809
DEBUG1(DBG_ATTACH, dip, "cb_ereport_post: elog 0x%lx",
usr/src/uts/sun4u/io/pci/pcisch.c
2844
DEBUG1(DBG_ERR_INTR, dip, "cb_ereport_post: ereport_set: %s", buf);
usr/src/uts/sun4u/io/pci/pcisch.c
2880
DEBUG1(DBG_ERR_INTR, dip, "iommu_ereport_post: ereport_set: %s", buf);
usr/src/uts/sun4u/io/pci/pcisch.c
2909
DEBUG1(DBG_ERR_INTR, dip, "pcix_ereport_post: ereport_post: %s", buf);
usr/src/uts/sun4u/io/pci/pcisch.c
3312
DEBUG1(DBG_INIT_CLD, child, "Turning on XMITS NCPQ "
usr/src/uts/sun4u/io/pci/pcisch.c
723
DEBUG1(DBG_ATTACH, dip, "pbm_configure: ctrl reg=%llx\n", l);
usr/src/uts/sun4u/io/pci/pcisch.c
739
DEBUG1(DBG_ATTACH, dip, "pbm_configure: %d mhz\n",
usr/src/uts/sun4u/io/pci/pcisch.c
850
DEBUG1(DBG_ATTACH, dip, "pbm_configure: ctrl reg=%llx\n", l);
usr/src/uts/sun4u/io/pci/pcisch.c
895
DEBUG1(DBG_ATTACH, dip, "pbm_configure: PCI diag reg=%llx\n", l);
usr/src/uts/sun4u/io/pci/pcisch.c
921
DEBUG1(DBG_ATTACH, dip, "pbm_configure: PCI diag reg=%llx\n", l);
usr/src/uts/sun4u/io/pci/pcisch.c
930
DEBUG1(DBG_ATTACH, dip, "pbm_configure: conf command reg=%x\n", s);
usr/src/uts/sun4u/io/pci/pcisch.c
939
DEBUG1(DBG_ATTACH, dip, "pbm_configure: conf status reg=%x\n", s);
usr/src/uts/sun4u/io/pci/pcisch.c
950
DEBUG1(DBG_ATTACH, dip,
usr/src/uts/sun4u/io/pci/pcisch.c
972
DEBUG1(DBG_ATTACH, dip, "pbm_configure: Setting XMITS"
usr/src/uts/sun4u/io/pci/pcix.c
60
DEBUG1(DBG_INIT_CLD, child, "pcix_set_cmd_reg: pcix_cap_ptr = %x\n",
usr/src/uts/sun4u/io/pci/pcix.c
70
DEBUG1(DBG_INIT_CLD, child, "pcix_set_cmd_reg: PCI-X CMD Register "
usr/src/uts/sun4u/io/pci/pcix.c
76
DEBUG1(DBG_INIT_CLD, child, "pcix_set_cmd_reg: PCI-X CMD Register "
usr/src/uts/sun4u/io/pci/simba.c
383
DEBUG1(D_ATTACH, "attach(%p) ATTACH\n", devi);
usr/src/uts/sun4u/io/pci/simba.c
643
DEBUG1(D_CTLOPS, "simba_ctlops(): *result=%lx\n", *(off_t *)result);
usr/src/uts/sun4u/io/pci/simba.c
706
DEBUG1(D_INIT_CLD, "simba_initchild(): child=%p\n", child);