nb_pci_putw
nb_pci_putw(0, 16, 1, 0xbe, 0))
nb_pci_putw(0, 16, 1, 0xd8, 0);
nb_pci_putw(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0xe0 : \
nb_pci_putw(0, 16, 1, 0xf8, 0); \
nb_pci_putw(0, 21, 0, 0xb0, val) : \
nb_pci_putw(0, 22, 0, 0xb0) : 0
nb_pci_putw(0, pex, 0, 0x144, val) : nb_pci_putl(0, pex, 0, 0x144, val))
#define PEX_ERR_PIN_MASK_WR(pex, val) nb_pci_putw(0, pex, 0, 0x146, val)
#define PEXROOTCTL_WR(pex, val) nb_pci_putw(0, pex, 0, 0x88, val)
#define PCISTS_WR(val) nb_pci_putw(0, 8, 0, 0x6, val)
#define PCIDEVSTS_WR(val) nb_pci_putw(0, 8, 0, 0x76, val)
#define EMASK_THR_WR(val) nb_pci_putw(0, 16, 2, 0xf6, val)
#define ERR0_THR_WR(val) nb_pci_putw(0, 16, 2, 0xf8, val)
#define ERR1_THR_WR(val) nb_pci_putw(0, 16, 2, 0xfa, val)
#define ERR2_THR_WR(val) nb_pci_putw(0, 16, 2, 0xfc, val)
#define MCERR_THR_WR(val) nb_pci_putw(0, 16, 2, 0xfe, val)
#define THRTSTS_WR(val) nb_pci_putw(0, 16, 3, 0x68, val)
nb_pci_putw(0, 17, ((fsb) & 2) ? 3 : 0, \
nb_pci_putw(0, 16, 0, fsb ? 0x492 : 0x192, val); \
nb_pci_putw(0, 17, (fsb & 2) ? 3 : 0, \
nb_pci_putw(0, 16, 0, fsb ? 0x494 : 0x194, val); \
nb_pci_putw(0, 17, (fsb & 2) ? 3 : 0, \
nb_pci_putw(0, 16, 0, fsb ? 0x496 : 0x196, val); \
nb_pci_putw(0, 17, (fsb & 2) ? 3 : 0, \
nb_pci_putw(0, 16, 0, fsb ? 0x498 : 0x198, val); \
nb_pci_putw(0, 17, (fsb & 2) ? 3 : 0, \
nb_pci_putw(0, 16, 0, fsb ? 0x49a : 0x19a, val); \
nb_pci_putw(0, (branch) ? 22 : 21, 1, 0xbe, 0) : \
nb_pci_putw(0, i, 0, PCI_CONF_COMM,
extern void nb_pci_putw(int, int, int, int, uint16_t);