nb_pci_putl
nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xc0, 0) : \
nb_pci_putl(0, 16, 1, 0xc0, 0))
nb_pci_putl(0, (branch) ? 22 : 21, 1, 0x74, 0); \
nb_pci_putl(0, 16, 1, 0x74, 0); \
nb_pci_putl(0, 16, 1, 0xc4, 0)
nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xc4, 0); \
nb_pci_putl(0, 16, 1, 0xc4, 0); \
nb_pci_putl(0, 16, 1, 0xc8, 0)
nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xc8, 0); \
nb_pci_putl(0, 16, 1, 0xc8, 0); \
nb_pci_putl(0, 16, 1, 0xcc, 0)
nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xcc, 0); \
nb_pci_putl(0, 16, 1, 0xcc, 0); \
nb_pci_putl(0, 16, 1, 0xd0, 0)
nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xd0, 0); \
nb_pci_putl(0, 16, 1, 0xd0, 0); \
nb_pci_putl(0, 16, 1, 0xd4, 0)
nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xd4, 0); \
nb_pci_putl(0, 16, 1, 0xd4, 0); \
nb_pci_putl(0, 16, 1, 0xd8, 0)
nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xd8, 0); \
nb_pci_putl(0, (branch) ? 22 : 21, 1, 0x7c, 0); \
nb_pci_putl(0, 16, 1, 0x7c, 0)
nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xe0, 0); \
nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xe4, 0); \
nb_pci_putl(0, 16, 1, 0xe4, 0)
nb_pci_putl(0, (branch) ? 22 : 21, 1, 0x78, 0); \
nb_pci_putl(0, 16, 1, 0x78, 0); \
nb_pci_putl(0, 16, 1, 0xe8, 0)
nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xe8, 0); \
nb_pci_putl(0, 16, 1, 0xe8, 0); \
nb_pci_putl(0, 16, 1, 0xec, 0)
nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xec, 0); \
nb_pci_putl(0, 16, 1, 0xec, 0); \
nb_pci_putl(0, 16, 1, 0xf0, 0)
nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xf0, 0); \
nb_pci_putl(0, 16, 1, 0xf0, 0); \
nb_pci_putl(0, 16, 1, 0xf4, 0)
nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xf4, 0); \
nb_pci_putl(0, 16, 1, 0xf4, 0); \
nb_pci_putl(0, 16, 1, 0xf8, 0)
nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xf8, 0); \
nb_pci_putl(0, 16, 1, 0xf8, 0); \
nb_pci_putl(0, 16, 1, 0xfc, 0)
nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xfc, 0); \
nb_pci_putl(0, 16, 1, 0xa0, (val))
nb_pci_putl(0, 16, 1, 0xa4, (val))
nb_pci_putl(0, 16, 1, 0xa8, (val))
nb_pci_putl(0, 16, 1, 0xac, (val))
nb_pci_putl(0, 16, 1, 0xb0, (val))
nb_pci_putl(0, 16, 1, 0xb4, (val))
nb_pci_putl(0, 16, 1, 0xb8, (val))
nb_pci_putl(0, (branch) ? 22 : 21, 0, 0x190, 0)
nb_pci_putl(0, (branch) ? 22 : 21, 0, 0x194, 0)
nb_pci_putl(0, (branch) ? 22 : 21, 0, 0x198, 0)
nb_pci_putl(0, (branch) ? 22 : 21, 0, 0x19c, 0)
nb_pci_putl(0, (branch) ? 22 : 21, 0, 0x1a0, 0)
nb_pci_putl(0, (branch) ? 22 : 21, 0, 0x1a4, 0)
#define MC_WR(val) nb_pci_putl(0, 16, 1, 0x40, val)
nb_pci_putl(0, 21, 0, 0xa4, val) : \
nb_pci_putl(0, 22, 0, 0xa4, val) \
nb_pci_putl(0, 21, 0, 0xa8, val) : \
nb_pci_putl(0, 22, 0, 0xa8, val) : 0
nb_pci_putl(0, 21, 0, 0xac, val) : \
nb_pci_putl(0, 22, 0, 0xac, val) : 0
nb_pci_putl(0, 21, 0, 0xb4, val) : \
nb_pci_putl(0, 22, 0, 0xb4, val) : 0
#define SPDCMD1_1_WR(val) nb_pci_putl(0, 21, 0, 0x7c, val)
nb_pci_putl(0, 16, 1, 0x4c, val); \
nb_pci_putl(0, 21, 0, 0x78 + ((channel) * 4), val); \
nb_pci_putl(0, 22, 0, 0x78 + ((channel) * 4), val)
#define UNCERRSTS_WR(pex, val) nb_pci_putl(0, pex, 0, 0x104, val)
#define UNCERRMSK_WR(pex, val) nb_pci_putl(0, pex, 0, 0x108, val)
#define PEX_FAT_FERR_ESI_WR(val) nb_pci_putl(0, 0, 0, 0x154, val)
#define PEX_FAT_NERR_ESI_WR(val) nb_pci_putl(0, 0, 0, 0x15c, val)
#define PEX_NF_FERR_ESI_WR(val) nb_pci_putl(0, 0, 0, 0x158, val)
#define PEX_NF_NERR_ESI_WR(val) nb_pci_putl(0, 0, 0, 0x160, val)
nb_pci_putw(0, pex, 0, 0x144, val) : nb_pci_putl(0, pex, 0, 0x144, val))
#define EMASK_UNCOR_PEX_WR(pex, val) nb_pci_putl(0, pex, 0, 0x148, val)
#define EMASK_COR_PEX_WR(pex, val) nb_pci_putl(0, pex, 0, 0x14c, val)
#define EMASK_RP_PEX_WR(pex, val) nb_pci_putl(0, pex, 0, 0x150, val)
#define PEX_FAT_FERR_WR(pex, val) nb_pci_putl(0, pex, 0, 0x154, val)
#define PEX_FAT_NERR_WR(pex, val) nb_pci_putl(0, pex, 0, 0x15c, val)
#define PEX_NF_FERR_WR(pex, val) nb_pci_putl(0, pex, 0, 0x158, val)
#define PEX_NF_NERR_WR(pex, val) nb_pci_putl(0, pex, 0, 0x160, val)
#define CORERRSTS_WR(pex, val) nb_pci_putl(0, pex, 0, 0x110, val)
#define UNCERRSEV_WR(pex, val) nb_pci_putl(0, pex, 0, 0x10c, val)
#define RPERRSTS_WR(pex, val) nb_pci_putl(0, pex, 0, 0x130, val)
#define PEXDEVSTS_WR(pex, val) nb_pci_putl(0, pex, 0, 0x76, val)
nb_pci_putl(0, 17, (fsb & 2) ? 3 : 0, (fsb & 1) ? 0xc4 : 0x44, \
nb_pci_putl(0, 16, 0, fsb ? 0x484 : 0x184, 0); \
nb_pci_putl(0, 17, (fsb & 2) ? 3 : 0, (fsb & 1) ? 0xc8 : 0x48, \
nb_pci_putl(0, 16, 0, fsb ? 0x488 : 0x188, 0); \
nb_pci_putl(0, 17, (fsb & 2) ? 3 : 0, (fsb & 1) ? 0xcc : 0x4c, \
nb_pci_putl(0, 16, 0, fsb ? 0x48c : 0x18c, 0); \
nb_pci_putl(0, 16, 2, 0x48, (uint32_t)(val >> 32)); \
nb_pci_putl(0, 16, 2, 0x40, (uint32_t)val); \
nb_pci_putl(0, 16, 2, 0x40, (uint32_t)val); \
#define NERR_GLOBAL_WR(val) nb_pci_putl(0, 16, 2, 0x44, val)
nb_pci_putl(0, 16, 2, 0xbc, 0); \
nb_pci_putl(0, 16, 2, 0xb0, 0); \
nb_pci_putl(0, 16, 2, 0xbc, 0); \
nb_pci_putl(0, 16, 2, 0xb8, 0); \
#define EMASK_5400_INT_WR(val) nb_pci_putl(0, 16, 2, 0xd0, val)
nb_pci_putl(0, 16, 2, 0xd4, val); \
nb_pci_putl(0, 16, 2, 0xd8, val); \
nb_pci_putl(0, 16, 2, 0xdc, val); \
nb_pci_putl(0, 16, 2, 0xe0, val); \
#define NRECINT_WR() nb_pci_putl(0, 16, 2, \
#define RECINT_WR() nb_pci_putl(0, 16, 2, \
#define FERR_FAT_FBD_WR(val) nb_pci_putl(0, 16, 1, 0x98, val)
#define NERR_FAT_FBD_WR(val) nb_pci_putl(0, 16, 1, 0x9c, val)
#define FERR_NF_FBD_WR(val) nb_pci_putl(0, 16, 1, 0xa0, val)
#define NERR_NF_FBD_WR(val) nb_pci_putl(0, 16, 1, 0xa4, val)
#define EMASK_FBD_WR(val) nb_pci_putl(0, 16, 1, 0xa8, val)
#define ERR0_FBD_WR(val) nb_pci_putl(0, 16, 1, 0xac, val)
#define ERR1_FBD_WR(val) nb_pci_putl(0, 16, 1, 0xb0, val)
#define ERR2_FBD_WR(val) nb_pci_putl(0, 16, 1, 0xb4, val)
#define MCERR_FBD_WR(val) nb_pci_putl(0, 16, 1, 0xb8, val)
extern void nb_pci_putl(int, int, int, int, uint32_t);