mwl_ctl_write4
mwl_ctl_write4(sc, MACREG_REG_A2H_INTERRUPT_CLEAR_SEL,
mwl_ctl_write4(sc, MACREG_REG_A2H_INTERRUPT_CAUSE, 0x00);
mwl_ctl_write4(sc, MACREG_REG_A2H_INTERRUPT_MASK, 0x00);
mwl_ctl_write4(sc, MACREG_REG_A2H_INTERRUPT_STATUS_MASK,
mwl_ctl_write4(sc, MACREG_REG_INT_CODE, 0);
mwl_ctl_write4(sc, MACREG_REG_GEN_PTR, OpMode);
mwl_ctl_write4(sc, MACREG_REG_INT_CODE, 0x00);
mwl_ctl_write4(sc, MACREG_REG_GEN_PTR, sc->sc_cmd_dmaaddr);
mwl_ctl_write4(sc, MACREG_REG_H2A_INTERRUPT_EVENTS,
mwl_ctl_write4(sc, MACREG_REG_PROMISCUOUS, ena ? v | 1 : v & ~1);
mwl_ctl_write4(sc, MACREG_REG_H2A_INTERRUPT_EVENTS,
mwl_ctl_write4(sc, MACREG_REG_A2H_INTERRUPT_MASK, 0);
mwl_ctl_write4(sc, MACREG_REG_A2H_INTERRUPT_MASK, mask);
mwl_ctl_write4(sc, MACREG_REG_A2H_INTERRUPT_CAUSE,
mwl_ctl_write4(sc, MACREG_REG_H2A_INTERRUPT_EVENTS, ISR_RESET);
mwl_ctl_write4(sc, 0x00006014, 0x33);
mwl_ctl_write4(sc, 0x00006018, 0xa3a2632);
mwl_ctl_write4(sc, 0x00006010, SDRAMSIZE_Addr);
mwl_ctl_write4(sc, MACREG_REG_GEN_PTR, sc->sc_cmd_dmaaddr);
mwl_ctl_write4(sc, MACREG_REG_INT_CODE, 0x00);
mwl_ctl_write4(sc, MACREG_REG_H2A_INTERRUPT_EVENTS,
mwl_ctl_write4(sc, MACREG_REG_INT_CODE, 0);
mwl_ctl_write4(sc, MACREG_REG_INT_CODE, 0);