mm_read_pci
(void) mm_read_pci(
lm_status = mm_read_pci(
lm_status = mm_read_pci(
lm_status = mm_read_pci(
lm_status = mm_read_pci(
lm_status = mm_read_pci(
lm_status = mm_read_pci(
lm_status = mm_read_pci(
lm_status = mm_read_pci(
lm_status = mm_read_pci(
mm_read_pci(
lm_status_t mm_read_pci(struct _lm_device_t *pdev,
mm_read_pci(pdev, 0, &pcicfg_chip);
lm_status = mm_read_pci(pdev, PCICFG_DEVICE_CONTROL, &val);
lm_status = mm_read_pci(pdev, PCICFG_VENDOR_ID_OFFSET, &val);
lm_status = mm_read_pci(pdev, PCICFG_SUBSYSTEM_VENDOR_ID_OFFSET, &val);
lm_status = mm_read_pci(pdev, PCICFG_INT_LINE, &val);
lm_status = mm_read_pci(pdev, PCICFG_CACHE_LINE_SIZE, &val);
lm_status = mm_read_pci(pdev, PCICFG_REVISION_ID_OFFSET, &val);
lm_status = mm_read_pci(pdev, PCICFG_LINK_CONTROL, &val);
mm_read_pci(pdev, pcie_caps_offset + PCIE_DEV_CTRL, &dev_control_and_status);
lm_status = mm_read_pci(pdev, pci_reg, &val);
lm_status = mm_read_pci(pdev, pci_reg, &val);
mm_read_pci(pdev, pdev->hw_info.pcie_caps_offset + PCIE_DEV_CAPS, &pdev->hw_info.pcie_dev_capabilities);
lm_status = mm_read_pci(pdev, PCICFG_VENDOR_ID_OFFSET, &pdev->hw_info.pci_cfg_didvid);
mm_read_pci(pdev,PCICFG_GRC_DATA,ret);
mm_read_pci(pdev, pcie_caps_offset + PCIE_DEV_CTRL, &dev_control_and_status);
mm_read_pci(
mm_read_pci(pdev, PCICFG_ME_REGISTER, &val);
lm_status_t lm_status = mm_read_pci(pdev, cap_offset, ®_value);
lm_status = mm_read_pci(pdev, cap_offset, ®_value);