usr/src/uts/intel/io/mc-amd/mcamd_drv.c

167

r1[i] = mc_pcicfg_get32(cfghdl, r1addr);

usr/src/uts/intel/io/mc-amd/mcamd_drv.c

169

r2[i] = mc_pcicfg_get32(cfghdl, r2addr);

usr/src/uts/intel/io/mc-amd/mcamd_drv.c

656

mc_pcicfg_get32(cfghdl, MC_HT_REG_NODEID);

usr/src/uts/intel/io/mc-amd/mcamd_drv.c

658

mc->mc_cfgregs.mcr_htunitid = mc_pcicfg_get32(cfghdl, MC_HT_REG_UNITID);

usr/src/uts/intel/io/mc-amd/mcamd_drv.c

663

mc->mc_cfgregs.mcr_htroute[i] = mc_pcicfg_get32(cfghdl, offset);

usr/src/uts/intel/io/mc-amd/mcamd_drv.c

688

mcr->mcr_drambase = MCREG_VAL32(&basereg) = mc_pcicfg_get32(cfghdl,

usr/src/uts/intel/io/mc-amd/mcamd_drv.c

691

mcr->mcr_dramlimit = MCREG_VAL32(&limreg) = mc_pcicfg_get32(cfghdl,

usr/src/uts/intel/io/mc-amd/mcamd_drv.c

716

mc_pcicfg_get32(cfghdl, MC_AM_REG_HOLEADDR);

usr/src/uts/intel/io/mc-amd/mcamd_drv.c

803

MCREG_VAL32(&drcfg_lo) = mc_pcicfg_get32(cfghdl, MC_DC_REG_DRAMCFGLO);

usr/src/uts/intel/io/mc-amd/mcamd_drv.c

804

MCREG_VAL32(&drcfg_hi) = mc_pcicfg_get32(cfghdl, MC_DC_REG_DRAMCFGHI);

usr/src/uts/intel/io/mc-amd/mcamd_drv.c

826

mc_pcicfg_get32(cfghdl, MC_DC_REG_DRAMMISC);

usr/src/uts/intel/io/mc-amd/mcamd_drv.c

839

mc_pcicfg_get32(cfghdl, MC_DC_REG_BANKADDRMAP);

usr/src/uts/intel/io/mc-amd/mcamd_pcicfg.h

46

extern uint32_t mc_pcicfg_get32(mc_pcicfg_hdl_t, off_t);