DBG_PWR
PCIEB_DEBUG(DBG_PWR, dip, "pcieb_pwr_setup: pci_config_setup "
PCIEB_DEBUG(DBG_PWR, dip, "switch/bridge does not support PM. "
PCIEB_DEBUG(DBG_PWR, dip, "D1 state supported\n");
PCIEB_DEBUG(DBG_PWR, dip, "D2 state supported\n");
PCIEB_DEBUG(DBG_PWR, dip, "could not create pm-components "
PCIEB_DEBUG(DBG_PWR, dip, "pcieb_pwr_setup: could not "
PCIEB_DEBUG(DBG_PWR, dip, "pcieb_pwr_disable: disabling PM\n");
PCIEB_DEBUG(DBG_PWR, devi, "pwr_common_setup failed\n");
PCIEB_DEBUG(DBG_PWR, devi, "pxb_pwr_setup failed \n");
PCIEB_DEBUG(DBG_PWR, pcieb->pcieb_dip,
PCIEB_DEBUG(DBG_PWR, ddi_get_parent(child),
PCIEB_DEBUG(DBG_PWR, ddi_get_parent(child),
DBG(DBG_PWR, dip, "PRE_ATTACH for %s@%d\n",
DBG(DBG_PWR, dip, "PRE_RESUME for %s@%d\n",
DBG(DBG_PWR, dip, "POST_ATTACH for %s@%d\n",
DBG(DBG_PWR, dip, "POST_DETACH for %s@%d\n",
DBG(DBG_PWR, dip, "pwr_common_setup failed\n");
DBG(DBG_PWR, dip, "px_pwr_setup failed \n");
DBG(DBG_PWR, dip, "can't create kernel ioctl prop\n");
DBG(DBG_PWR, dip, "px_pwr_setup: couldn't add "
DBG(DBG_PWR, dip, "px_pwr_setup: PME_TO_ACK update interrupt"
DBG(DBG_PWR, ddi_get_parent(child), "\n\n");
DBG(DBG_PWR, parent_dip,
DBG(DBG_PWR, child,
DBG(DBG_PWR, parent_dip,
{DBG_PWR, "pwr"},
DEBUG2(DBG_PWR, ddi_get_parent(dip),
DEBUG0(DBG_PWR, pdip, "bridge does not support PM. PCI"
DEBUG0(DBG_PWR, pdip, "setup: B1 state supported\n");
DEBUG0(DBG_PWR, pdip, "setup: B1 state NOT supported\n");
DEBUG0(DBG_PWR, pdip, "setup: B2 state supported\n");
DEBUG0(DBG_PWR, pdip, "setup: B2 via D2 NOT supported\n");
DEBUG0(DBG_PWR, pdip,
DEBUG0(DBG_PWR, pdip,
DEBUG0(DBG_PWR, pdip, "B2 supported via D3\n");
DEBUG0(DBG_PWR, pdip, "B3 supported via D3\n");
DEBUG1(DBG_PWR, dip, "ppb_pwr(): ENTER level = %d\n", lvl);
DEBUG2(DBG_PWR, dip, "ppb_pwr: failing power request "
DEBUG0(DBG_PWR, dip, "ppb_pwr(): SAVING CONFIG REGS\n");
DEBUG0(DBG_PWR, dip, "ppb_pwr(): RESTORING CONFIG REGS\n");
DEBUG1(DBG_PWR, dip, "ppb_set_pwr: set PM state to %s\n\n", str);
DEBUG2(DBG_PWR, ddi_get_parent(child),
DEBUG2(DBG_PWR, ddi_get_parent(child),
DEBUG3(DBG_PWR, ddi_get_parent(cdip),
DEBUG1(DBG_PWR, pwr_p->pwr_dip, "new_lvl: "
DEBUG1(DBG_PWR, pwr_p->pwr_dip, "new_lvl: unknown "
DEBUG1(DBG_PWR, pwr_p->pwr_dip,
DEBUG1(DBG_PWR, pwr_p->pwr_dip,
DEBUG1(DBG_PWR, pwr_p->pwr_dip,
DEBUG1(DBG_PWR, pwr_p->pwr_dip,
DEBUG0(DBG_PWR, pwr_p->pwr_dip,
DEBUG1(DBG_PWR, pwr_p->pwr_dip,
DEBUG5(DBG_PWR, dip, "%s@%s CHANGED_POWER cmp = %d "
DEBUG0(DBG_PWR, rdip, "changed_power_req FAILED\n");
DEBUG5(DBG_PWR, dip, "PRE %s@%s cmp = %d old = %d "
DEBUG1(DBG_PWR, pwr_p->pwr_dip,
DEBUG5(DBG_PWR, dip, "POST %s@%s cmp = %d old = %d new = %d\n",
DEBUG0(DBG_PWR, rdip, "child's power routine FAILED\n");
DEBUG1(DBG_PWR, pwr_p->pwr_dip,
DEBUG2(DBG_PWR, dip,
DEBUG0(DBG_PWR, p->pwr_dip,
DEBUG0(DBG_PWR, p->pwr_dip, "BUSY BIT ALREADY SET\n");
DEBUG0(DBG_PWR, p->pwr_dip,
DEBUG0(DBG_PWR, p->pwr_dip, "BUSY BIT ALREADY CLEARED\n");
DEBUG2(DBG_PWR, pwr_p->pwr_dip,
DEBUG2(DBG_PWR, pwr_p->pwr_dip,
DEBUG2(DBG_PWR, pwr_p->pwr_dip, "pwr_change: "
DEBUG2(DBG_PWR, ddi_get_parent(dip), "ADDING NEW PWR_INFO %s@%s\n",
DEBUG0(DBG_PWR, ddi_get_parent(child), "\n\n");
DEBUG0(DBG_PWR, child,
DEBUG2(DBG_PWR, ddi_get_parent(child),
DEBUG2(DBG_PWR, dip,
DEBUG0(DBG_PWR, dip, "quiescing bus\n");
DBG(DBG_PWR, NULL, "send_pme_turnoff: pending PTO bit "
DBG(DBG_PWR, NULL, "check_for_l1idle: ltssm_state %x\n", ltssm_state);
DBG(DBG_PWR, NULL, "retrain_link: detect.quiet bit not set\n");
DBG(DBG_PWR, px_p->px_dip,
DBG(DBG_PWR, px_p->px_dip, "ioctl: PRE_PWR_ON request\n");
DBG(DBG_PWR, px_p->px_dip, "ioctl: POST_PWR_ON request\n");
DBG(DBG_PWR, px_p->px_dip, " Timed out while waiting"
DBG(DBG_PWR, px_p->px_dip, " Link is not at L1"
DBG(DBG_PWR, px_p->px_dip, " PME_To_ACK received \n");