DBG_MSIQ
DBG(DBG_MSIQ, dip, "px_add_msiq_intr: rdip=%s%d handler=0x%x "
DBG(DBG_MSIQ, dip, "px_add_msiq_intr: "
DBG(DBG_MSIQ, dip, "px_add_msiq_intr: "
DBG(DBG_MSIQ, dip, "px_add_msiq_intr: pil=0x%x mondo=0x%x\n",
DBG(DBG_MSIQ, dip, "px_add_msiq_intr: done! Interrupt 0x%x pil=%x\n",
DBG(DBG_MSIQ, dip, "px_add_msiq_intr: Failed! Interrupt 0x%x pil=%x\n",
DBG(DBG_MSIQ, dip, "px_rem_msiq_intr: rdip=%s%d msiq_id=%x ino=%x\n",
DBG(DBG_MSIQ, dip, "px_msi_detach\n");
DBG(DBG_MSIQ, dip, "px_msi_get_props\n");
DBG(DBG_MSIQ, dip, "#msi=%d\n", msi_state_p->msi_cnt);
DBG(DBG_MSIQ, dip, "msi_1st_msinum=%d\n", msi_state_p->msi_1st_msinum);
DBG(DBG_MSIQ, dip, "msi-data-mask=0x%x\n",
DBG(DBG_MSIQ, dip, "msix-data-width=%d\n",
DBG(DBG_MSIQ, dip, "msi_addr32=0x%llx\n", msi_state_p->msi_addr32);
DBG(DBG_MSIQ, dip, "msi_addr64=0x%llx\n", msi_state_p->msi_addr64);
DBG(DBG_MSIQ, dip, "px_msi_attach\n");
DBG(DBG_MSIQ, dip, "ndi_irm_create() failed\n");
DBG(DBG_MSIQ, px_p->px_dip, "px_msiq_detach\n");
DBG(DBG_MSIQ, px_p->px_dip,
DBG(DBG_MSIQ, px_p->px_dip, "px_msiq_alloc\n");
DBG(DBG_MSIQ, px_p->px_dip,
DBG(DBG_MSIQ, px_p->px_dip,
DBG(DBG_MSIQ, px_p->px_dip, "px_msiq_alloc_based_on_cpuid: "
DBG(DBG_MSIQ, px_p->px_dip,
DBG(DBG_MSIQ, px_p->px_dip,
DBG(DBG_MSIQ, px_p->px_dip, "px_msiq_free: msiq_id 0x%x", msiq_id);
DBG(DBG_MSIQ, px_p->px_dip,
DBG(DBG_MSIQ, px_p->px_dip, "px_msiq_redist: "
DBG(DBG_MSIQ, px_p->px_dip, "px_msiqid_to_devino: "
DBG(DBG_MSIQ, px_p->px_dip, "px_devino_to_msiq: "
DBG(DBG_MSIQ, px_p->px_dip, "px_msiq_get_props\n");
DBG(DBG_MSIQ, px_p->px_dip, "msiq_cnt=%d\n", msiq_state_p->msiq_cnt);
DBG(DBG_MSIQ, px_p->px_dip, "msiq_rec_cnt=%d\n",
DBG(DBG_MSIQ, px_p->px_dip, "msi-eq-to-devino is not found\n");
DBG(DBG_MSIQ, px_p->px_dip, "msiq_1st_msiq_id=%d\n",
DBG(DBG_MSIQ, px_p->px_dip, "msiq_1st_devino=%d\n",
DBG(DBG_MSIQ, px_p->px_dip, "px_msiq_attach\n");