DBG_IB
DBG(DBG_IB, px_p->px_dip,
DBG(DBG_IB, px_p->px_dip,
DBG(DBG_IB, ib_p->ib_px_p->px_dip, "px_ib_intr_disable: ino=%x\n", ino);
DBG(DBG_IB, ib_p->ib_px_p->px_dip,
DBG(DBG_IB, dip, "px_ib_intr_dist_en: ino=0x%x\n", ino);
DBG(DBG_IB, dip, "px_ib_intr_dist_en: "
DBG(DBG_IB, dip, "px_ib_intr_dist_en: px_intr_getvalid() "
DBG(DBG_IB, dip, "px_ib_intr_dist_en: "
DBG(DBG_IB, dip, "px_ib_intr_dist_en: failed, "
DBG(DBG_IB, dip, "px_ib_intr_redist: sysino 0x%llx "
DBG(DBG_IB, dip, "px_ib_intr_redist: sysino 0x%llx "
DBG(DBG_IB, ib_p->ib_px_p->px_dip, "px_ib_intr_reset\n");
DBG(DBG_IB, dip, "px_ib_attach\n");
DBG(DBG_IB, dip, "px_ib_ino_add_intr ino=%x\n", ino_p->ino_ino);
DBG(DBG_IB, dip,
DBG(DBG_IB, dip, "px_ib_ino_add_intr: failed, "
DBG(DBG_IB, px_p->px_dip, "px_ib_ino_rem_intr ino=%x\n",
DBG(DBG_IB, dip, "px_ib_ino_rem_intr: failed, "
DBG(DBG_IB, px_p->px_dip, "px_ib_update_intr_state: %s%d "
DBG(DBG_IB, px_p->px_dip, "px_ib_get_intr_target: devino %x\n", ino);
DBG(DBG_IB, px_p->px_dip, "px_ib_get_intr_target: cpu_id %x\n",
DBG(DBG_IB, px_p->px_dip, "px_ib_set_intr_target: devino %x "
DBG(DBG_IB, dip, "px_ib_set_intr_target: Enabling CPU %d\n",
DBG(DBG_IB, dip, "px_ib_set_intr_target: Invalid cpuid %x\n",
DBG(DBG_IB, dip, "px_ib_set_msix_target: msi_num %x new cpu_id %x\n",
DBG(DBG_IB, dip, "px_ib_set_msix_target: current msiq 0x%x\n",
DBG(DBG_IB, dip, "px_ib_set_msix_target: current cpuid 0x%x\n",
DBG(DBG_IB, dip, "px_ib_set_msix_target: Invalid cpuid %x\n",
DBG(DBG_IB, dip, "px_ib_detach\n");
DBG(DBG_IB, dip, "px_ib_set_msix_target: Enabling CPU %d\n", cpu_id);
DBG(DBG_IB, dip, "px_ib_set_msix_target: Add MSI handler "
DBG(DBG_IB, dip,
{DBG_IB, "ib"},
DEBUG0(DBG_IB, dip, "ib_destroy\n");
DEBUG2(DBG_IB, pci_p->pci_dip,
DEBUG0(DBG_IB, ib_p->ib_pci_p->pci_dip,
DEBUG1(DBG_IB, dip, "ib_get_intr_target: ino %x\n", ino);
DEBUG1(DBG_IB, dip, "ib_get_intr_target: cpu_id %x\n", *cpu_id_p);
DEBUG2(DBG_IB, dip, "ib_set_intr_target: ino %x cpu_id %x\n",
DEBUG1(DBG_IB, dip, "ib_set_intr_target: orig mapreg value: 0x%llx\n",
DEBUG0(DBG_IB, dip, "Clearing intr_enabled...\n");
DEBUG0(DBG_IB, dip, "About to check for pending interrupts...\n");
DEBUG0(DBG_IB, dip, "Waiting for pending ints to clear\n");
DEBUG0(DBG_IB, dip, "Timed out waiting \n");
DEBUG1(DBG_IB, dip,
DEBUG1(DBG_IB, dip, "Writing new mapreg value:0x%llx\n",
DEBUG0(DBG_IB, dip,
DEBUG3(DBG_IB, dip, "pci_xlate_intr: bus=%x, dev=%x, intr=%x\n",
DEBUG1(DBG_IB, dip, "pci_xlate_intr: done ino=%x\n", intr);
DBG(DBG_IB, NULL, "ino %x is invalid\n", devino);
DBG(DBG_IB, NULL,
DBG(DBG_IB, NULL, "hvio_msiq_init: "
DBG(DBG_IB, NULL, "hvio_msi_init: MSI_32_BIT_ADDRESS: 0x%llx\n",
DBG(DBG_IB, NULL, "hvio_msi_init: MSI_64_BIT_ADDRESS: 0x%llx\n",
DBG(DBG_IB, NULL, "hvio_ib_init - IMU_ERROR_LOG_ENABLE: 0x%llx\n",
DBG(DBG_IB, NULL, "hvio_ib_init - IMU_INTERRUPT_ENABLE: 0x%llx\n",
DBG(DBG_IB, NULL, "hvio_ib_init - IMU_INTERRUPT_STATUS: 0x%llx\n",
DBG(DBG_IB, NULL, "hvio_ib_init - IMU_ERROR_STATUS_CLEAR: 0x%llx\n",
DBG(DBG_IB, pxp->px_dip, "px_cb_intr_redist: CB not enabled, "