usr/src/uts/common/io/iwp/iwp.c

289

static void iwp_reg_write(iwp_sc_t *, uint32_t, uint32_t);

usr/src/uts/common/io/iwp/iwp.c

4298

iwp_reg_write(sc, ALM_APMG_PS_CTL, tmp);

usr/src/uts/common/io/iwp/iwp.c

4345

iwp_reg_write(sc, ALM_APMG_CLK_EN, APMG_CLK_REG_VAL_DMA_CLK_RQT);

usr/src/uts/common/io/iwp/iwp.c

4349

iwp_reg_write(sc, ALM_APMG_PCIDEV_STT, tmp |

usr/src/uts/common/io/iwp/iwp.c

4395

iwp_reg_write(sc, ALM_APMG_PS_CTL, tmp);

usr/src/uts/common/io/iwp/iwp.c

4400

iwp_reg_write(sc, ALM_APMG_PS_CTL, tmp);

usr/src/uts/common/io/iwp/iwp.c

4694

iwp_reg_write(sc, ALM_APMG_CLK_DIS, APMG_CLK_REG_VAL_DMA_CLK_RQT);

usr/src/uts/common/io/iwp/iwp.c

4940

iwp_reg_write(sc, IWP_SCD_DRAM_BASE_ADDR,

usr/src/uts/common/io/iwp/iwp.c

4943

iwp_reg_write(sc, IWP_SCD_QUEUECHAIN_SEL,

usr/src/uts/common/io/iwp/iwp.c

4946

iwp_reg_write(sc, IWP_SCD_AGGR_SEL, 0);

usr/src/uts/common/io/iwp/iwp.c

4949

iwp_reg_write(sc, IWP_SCD_QUEUE_RDPTR(i), 0);

usr/src/uts/common/io/iwp/iwp.c

4963

iwp_reg_write(sc, IWP_SCD_INTERRUPT_MASK, (1 << IWP_NUM_QUEUES) - 1);

usr/src/uts/common/io/iwp/iwp.c

4965

iwp_reg_write(sc, (IWP_SCD_BASE + 0x10),

usr/src/uts/common/io/iwp/iwp.c

4969

iwp_reg_write(sc, IWP_SCD_QUEUE_RDPTR(IWP_CMD_QUEUE_NUM), 0);

usr/src/uts/common/io/iwp/iwp.c

4976

iwp_reg_write(sc, IWP_SCD_QUEUE_STATUS_BITS(i),

usr/src/uts/common/io/iwp/iwp.c

4983

iwp_reg_write(sc, IWP_SCD_QUEUE_STATUS_BITS(IWP_CMD_QUEUE_NUM),

usr/src/uts/common/io/iwp/iwp.c

4990

iwp_reg_write(sc, IWP_SCD_QUEUE_STATUS_BITS(i),

usr/src/uts/common/io/iwp/iwp.c

5183

iwp_reg_write(sc, IWP_SCD_TXFACT, 0);