usr/src/uts/common/io/iwh/iwh.c

297

static void iwh_reg_write(iwh_sc_t *, uint32_t, uint32_t);

usr/src/uts/common/io/iwh/iwh.c

4566

iwh_reg_write(sc, ALM_APMG_PS_CTL, tmp);

usr/src/uts/common/io/iwh/iwh.c

4616

iwh_reg_write(sc, ALM_APMG_CLK_EN, APMG_CLK_REG_VAL_DMA_CLK_RQT);

usr/src/uts/common/io/iwh/iwh.c

4620

iwh_reg_write(sc, ALM_APMG_PCIDEV_STT, tmp |

usr/src/uts/common/io/iwh/iwh.c

4666

iwh_reg_write(sc, ALM_APMG_PS_CTL, tmp);

usr/src/uts/common/io/iwh/iwh.c

4671

iwh_reg_write(sc, ALM_APMG_PS_CTL, tmp);

usr/src/uts/common/io/iwh/iwh.c

4957

iwh_reg_write(sc, ALM_APMG_CLK_DIS, APMG_CLK_REG_VAL_DMA_CLK_RQT);

usr/src/uts/common/io/iwh/iwh.c

5324

iwh_reg_write(sc, IWH_SCD_DRAM_BASE_ADDR,

usr/src/uts/common/io/iwh/iwh.c

5327

iwh_reg_write(sc, IWH_SCD_QUEUECHAIN_SEL,

usr/src/uts/common/io/iwh/iwh.c

5330

iwh_reg_write(sc, IWH_SCD_AGGR_SEL, 0);

usr/src/uts/common/io/iwh/iwh.c

5333

iwh_reg_write(sc, IWH_SCD_QUEUE_RDPTR(i), 0);

usr/src/uts/common/io/iwh/iwh.c

5347

iwh_reg_write(sc, IWH_SCD_INTERRUPT_MASK, (1 << IWH_NUM_QUEUES) - 1);

usr/src/uts/common/io/iwh/iwh.c

5349

iwh_reg_write(sc, (IWH_SCD_BASE + 0x10),

usr/src/uts/common/io/iwh/iwh.c

5353

iwh_reg_write(sc, IWH_SCD_QUEUE_RDPTR(IWH_CMD_QUEUE_NUM), 0);

usr/src/uts/common/io/iwh/iwh.c

5360

iwh_reg_write(sc, IWH_SCD_QUEUE_STATUS_BITS(i),

usr/src/uts/common/io/iwh/iwh.c

5367

iwh_reg_write(sc, IWH_SCD_QUEUE_STATUS_BITS(IWH_CMD_QUEUE_NUM),

usr/src/uts/common/io/iwh/iwh.c

5374

iwh_reg_write(sc, IWH_SCD_QUEUE_STATUS_BITS(i),

usr/src/uts/common/io/iwh/iwh.c

5649

iwh_reg_write(sc, IWH_SCD_TXFACT, 0);