isr
pxe_netif_receive_isr(t_PXENV_UNDI_ISR *isr, void **pkt, ssize_t *retsize)
bzero(isr, sizeof (*isr));
isr->FuncFlag = PXENV_UNDI_ISR_IN_START;
pxe_call(PXENV_UNDI_ISR, isr);
if (isr->Status != 0) {
bzero(isr, sizeof (*isr));
isr->FuncFlag = PXENV_UNDI_ISR_IN_PROCESS;
pxe_call(PXENV_UNDI_ISR, isr);
if (isr->Status != 0) {
if (isr->FuncFlag == PXENV_UNDI_ISR_OUT_BUSY) {
while (isr->FuncFlag != PXENV_UNDI_ISR_OUT_DONE) {
if (isr->FuncFlag != PXENV_UNDI_ISR_OUT_RECEIVE)
size = isr->FrameLength;
frame = (char *)((uintptr_t)isr->Frame.segment << 4);
frame += isr->Frame.offset;
bcopy(PTOV(frame), ptr, isr->BufferLength);
ptr += isr->BufferLength;
rsize += isr->BufferLength;
bzero(isr, sizeof (*isr));
isr->FuncFlag = PXENV_UNDI_ISR_IN_GET_NEXT;
pxe_call(PXENV_UNDI_ISR, isr);
if (isr->Status != 0) {
t_PXENV_UNDI_ISR *isr;
isr = bio_alloc(sizeof (*isr));
if (isr == NULL)
ret = pxe_netif_receive_isr(isr, pkt, size);
bio_free(isr, sizeof (*isr));
vi_interrupt(struct virtio_softc *vs, uint8_t isr, uint16_t msix_idx)
vs->vs_isr |= isr;
u32 isr = readl(ns->base + ISR);
if(ISR_PHY & isr)
if(( ISR_RXIDLE | ISR_RXDESC | ISR_RXERR) & isr)
u32 isr = readl(ns->base + ISR);
if (ISR_TXIDLE & isr)
status ^= (inl(isr + ioaddr) & status);
GCC_ATTR(isr)
uint32_t isr = 0;
isr = REG_READ(ah, AR_ISR);
if (!isr && !sync_cause)
isr = REG_READ(ah, AR_ISR);
if (isr) {
if (isr & AR_ISR_BCNMISC) {
isr = REG_READ(ah, AR_ISR_RAC);
if (isr == 0xffffffff) {
*masked = isr & ATH9K_INT_COMMON;
if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
if (isr &
if (isr & AR_ISR_RXORN) {
int isr, lsr, mcr, spr;
isr = asy_get(asy, ASY_ISR);
if (isr == 0xff) {
asy->asy_fifor | ASY_FCR_THR_FL | ASY_FCR_RHR_FL, isr, mcr);
switch (isr & (ASY_ISR_FIFOEN | ASY_ISR_FIFO64)) {
asy->asy_fifor | ASY_FCR_THR_FL | ASY_FCR_RHR_FL, isr, mcr);
(caddr_t *)&cpqary3p->isr, (offset_t)I2O_INT_STATUS, map_len,
uint32_t *isr;
(uint32_t *)cpqary3p->isr))) {
(ddi_get32(cpqary3p->isr_handle, (uint32_t *)cpqary3p->isr)))
(uint32_t *)cpqary3p->isr))) {
static void rtw_ring_recycling(rtw_softc_t *rsc, uint16_t isr, uint32_t pri);
rtw_ring_recycling(rtw_softc_t *rsc, uint16_t isr, uint32_t pri)
(hstat & RTW_TXSTAT_DRC_MASK), isr, cnt);
uint16_t isr = 0;
isr = RTW_READ16(regs, RTW_ISR);
RTW_WRITE16(regs, RTW_ISR, isr);
if (isr == 0) {
if ((isr & flag) != 0) { \
if ((rtw_dbg_flags & RTW_DEBUG_INTR) != 0 && isr != 0) {
RTW_DPRINTF(RTW_DEBUG_INTR, "rtw: reg[ISR] = %x", isr);
if ((isr & RTW_INTR_RX) != 0) {
if ((isr & RTW_INTR_TIMEOUT) != 0)
if ((isr & RTW_INTR_TX) != 0)
rtw_ring_recycling(rsc, isr, 1);
uint32_t isr = smrt_get32(smrt, CISS_I2O_INTERRUPT_STATUS);
if ((isr & CISS_ISR_BIT_SIMPLE_INTR) == 0) {
uint32_t isr;
isr = INL(dp, ISR);
if (((isr | isr_bogus) & lp->our_intr_bits) == 0) {
isr, INTR_BITS, dp->rx_active_head));
isr &= lp->our_intr_bits;
if (isr & (ISR_RXSOVR | ISR_RXORN | ISR_RXIDLE | ISR_RXERR |
if (isr & (ISR_RXSOVR | ISR_RXORN)) {
dp->name, isr, INTR_BITS));
if (isr & ISR_RXIDLE) {
dp->name, isr, INTR_BITS));
if (isr & (ISR_TXURN | ISR_TXERR | ISR_TXDESC |
if (isr & (ISR_DPERR | ISR_SSERR | ISR_RMABT | ISR_RTABT)) {
dp->name, isr, INTR_BITS);
dp->name, __func__, isr, INTR_BITS));
uint8_t isr;
isr = vio->vio_ops->vop_isr_status(vio);
if ((isr & VIRTIO_ISR_CHECK_QUEUES) != 0) {
if ((isr & VIRTIO_ISR_CHECK_CONFIG) != 0) {
uint_t isr;
isr = apic_reg_ops->apic_read(APIC_ISR_REG + (i * 4));
if (isr != 0)
for (j = 0; ((j < 32) && (isr != 0)); j++)
if (isr & (1 << j)) {
isr &= ~(1 << j);
uint_t isr;
isr = apic_reg_ops->apic_read(APIC_ISR_REG + (i * 4));
if (isr != 0)
for (j = 0; ((j < 32) && (isr != 0)); j++)
if (isr & (1 << j)) {
isr &= ~(1 << j);
uint64_t isr; /* Interrupt Status */
if (vhpet->isr & (1 << n)) {
vhpet->isr &= ~(1 << n);
if ((vhpet->isr & (1 << n)) != 0) {
vhpet->isr |= 1 << n;
if (vhpet->isr & (1 << n))
if (vhpet->isr & (1 << n)) {
vhpet->isr &= ~(1 << n);
isr_clear_mask = vhpet->isr & data;
data = vhpet->isr;
out->vh_isr = vhpet->isr;
vhpet->isr = src->vh_isr;