ipltospl
lock_set_spl(lp, ipltospl(DISP_LEVEL), &curthread->t_oldspl);
mutex_init(&reaplock, NULL, MUTEX_SPIN, (void *)ipltospl(DISP_LEVEL));
mutex_init(&lat->ly_mutex, NULL, MUTEX_SPIN, (void *)ipltospl(SPL7));
mutex_init(&srq->srq_mutex, NULL, MUTEX_SPIN, (void *)ipltospl(SPL7));
(void *)ipltospl(12));
(void *)ipltospl(LOCK_LEVEL)); \
(void *)ipltospl(LOCK_LEVEL));
(void *)ipltospl(LOCK_LEVEL));
(void *)ipltospl(LOCK_LEVEL));
(void *)ipltospl(LOCK_LEVEL));
(void *)ipltospl(LOCK_LEVEL));
(void *)ipltospl(LOCK_LEVEL));
(void *)ipltospl(LOCK_LEVEL));
(void *)ipltospl(LOCK_LEVEL));
ibc = (ddi_iblock_cookie_t)ipltospl(FM_ERR_PIL);
ddi_iblock_cookie_t ibc = (ddi_iblock_cookie_t)(uintptr_t)ipltospl(ipl);
(ddi_iblock_cookie_t)(uintptr_t)ipltospl(eqp->eq_ipl);
log_freeq = log_makeq(LOG_MINFREE, LOG_MAXFREE, (void *)ipltospl(SPL8));
log_intrq = log_makeq(0, LOG_HIWAT, (void *)ipltospl(SPL8));
if ((intptr_t)ibc > ipltospl(LOCK_LEVEL) && ibc < (void *)KERNELBASE) {
splx(ipltospl(CLOCK_LEVEL));
splx(ipltospl(CLOCK_LEVEL));
splx(MIN(s, ipltospl(CLOCK_LEVEL)));
(void *)ipltospl(SPL8));
mutex_init(&pm_cfb_lock, NULL, MUTEX_SPIN, (void *)ipltospl(SPL8));
mutex_init(&pm_debug_lock, NULL, MUTEX_SPIN, (void *)ipltospl(SPL8));
lock_set_spl(&unix_bb_lock, ipltospl(NMI_LEVEL), &s);
mutex_init(&ec_lock, NULL, MUTEX_SPIN, (void *)ipltospl(SPL7));
splx(ipltospl(LOCK_LEVEL));
return (splr(ipltospl(ipl)));
s = splr(ipltospl(XC_HI_PIL));
(void *)ipltospl(IMMU_INTR_IPL));
(void *)ipltospl(IMMU_INTR_IPL));
splx(ipltospl(LOCK_LEVEL));
rootnex_state->r_err_ibc = (ddi_iblock_cookie_t)ipltospl(15);
(void *)ipltospl(DISP_LEVEL));
return (splr(ipltospl(XCALL_PIL)));
splx(ipltospl(CLOCK_LEVEL));
int save_spl = splr(ipltospl(XC_HI_PIL));
splx(ipltospl(LOCK_LEVEL));
ASSERT(cp->cpu_base_spl == ipltospl(LOCK_LEVEL));
cp->cpu_base_spl = ipltospl(LOCK_LEVEL);
(ddi_iblock_cookie_t)ipltospl(15));
(ddi_iblock_cookie_t)ipltospl(DISP_LEVEL));
(ddi_iblock_cookie_t)ipltospl(15));
ipltospl(CBE_HIGH_PIL), &spl);
save_spl = splr(ipltospl(XC_HI_PIL));
int save_spl = splr(ipltospl(XC_HI_PIL));
ipltospl(XC_HI_PIL), oldsplp)
mutex_init(&ec_lock, NULL, MUTEX_SPIN, (void *)ipltospl(SPL7));
(ddi_iblock_cookie_t)ipltospl(DISP_LEVEL));
return (ipltospl(ipl));
return (ipltospl(APIC_PCINT_IPL));
#define SPIN_LOCK(pl) ((pl) > ipltospl(LOCK_LEVEL))
(void *)ipltospl(DISP_LEVEL));
return (ipltospl(ipl));
#define SPIN_LOCK(pl) ((pl) > ipltospl(LOCK_LEVEL))
#define ZS_PL ipltospl(SPL3) /* translates to SPARC IPL 6 */
#define ZS_PL_HI ipltospl(SPLTTY) /* translates to SPARC IPL 12 */
if ((s = getpil()) < ipltospl(12))
mutex_init(&cpu_idle_lock, NULL, MUTEX_SPIN, (void *)ipltospl(PIL_15));
(void *)ipltospl(XCALL_PIL));
ipltospl(CBE_HIGH_PIL), oldsplp)
(void *)(uintptr_t)ipltospl(spltoipl(
(void *)ipltospl(XCALL_PIL));
(void *)ipltospl(XCALL_PIL));
(void *) ipltospl(FM_ERR_PIL));
(void *)ipltospl(SBUS_ERR_PIL - 1));
ipltospl(ds1287_interrupt_priority);
ipltospl(ds1287_softint_priority);
(void *)(uintptr_t)ipltospl(spltoipl(
if (spl == ipltospl(PIL_14)) {
} else if (spl == ipltospl(PIL_15)) {
if (spl == ipltospl(PIL_14)) {
} else if (spl == ipltospl(PIL_15)) {