C_AFSR_UE
C_AFSR_UE, "UE ", ECC_ASYNC_TRAPS, CPU_UE,
C_AFSR_UE | C_AFSR_EDU | C_AFSR_EMU | C_AFSR_WDU | C_AFSR_CPU,
C_AFSR_UE | C_AFSR_IVU | C_AFSR_EDU | C_AFSR_WDU | C_AFSR_UCU |
C_AFSR_UE, "UE ", ECC_ASYNC_TRAPS,
C_AFSR_UE | C_AFSR_DUE | C_AFSR_EDU | C_AFSR_EMU | C_AFSR_WDU |
C_AFSR_UE | C_AFSR_DUE | C_AFSR_IVU | C_AFSR_EDU | C_AFSR_EMU |
C_AFSR_UE | C_AFSR_DUE | C_AFSR_IVU | C_AFSR_EDU | C_AFSR_WDU |
if (t_afsr & (C_AFSR_UE|C_AFSR_RUE|C_AFSR_TO|C_AFSR_BERR)) {
if (t_afsr & (C_AFSR_UE|C_AFSR_RUE)) {
if (aflt->flt_panic && cpu_flt_in_memory(&ch_flt, C_AFSR_UE)) {
if (t_afsr & (C_AFSR_UE | C_AFSR_RUE | C_AFSR_EDU | C_AFSR_BERR))
if (t_afsr & (C_AFSR_UE|C_AFSR_TO|C_AFSR_BERR)) {
if (t_afsr & C_AFSR_UE) {
if (aflt->flt_panic && cpu_flt_in_memory(&ch_flt, C_AFSR_UE)) {
(C_AFSR_UE | C_AFSR_EDU | C_AFSR_BERR | C_AFSR_L3_EDU))
(C_AFSR_ALL_ERRS | C_AFSR_EXT_ALL_ERRS)) == C_AFSR_UE &&
if (afsr & (C_AFSR_UE|C_AFSR_RUE)) {
if ((afsr & C_AFSR_ALL_ERRS) == C_AFSR_UE ||
if (afsr_errs & C_AFSR_UE) {
C_AFSR_UE) {
if (t_afsr_errs != C_AFSR_UE)
case C_AFSR_UE:
C_AFSR_UE, "UE ", ECC_ASYNC_TRAPS, CPU_UE,
C_AFSR_UE | C_AFSR_RUE | C_AFSR_BP | C_AFSR_WBP | C_AFSR_EDU |
C_AFSR_UE,
C_AFSR_UE | C_AFSR_FRU | C_AFSR_EDU | C_AFSR_WDU | C_AFSR_UCU |
case C_AFSR_UE:
#define C_AFSR_ALL_ME_ERRS (C_AFSR_ISAP | C_AFSR_UE | C_AFSR_UCU | \
#define C_AFSR_ALL_ME_ERRS (C_AFSR_ISAP | C_AFSR_UE | C_AFSR_UCU | \
#define C_AFSR_MEMORY (C_AFSR_UE | C_AFSR_CE | C_AFSR_FRC | C_AFSR_FRU |\
#define C_AFSR_ESYND_ERRS (C_AFSR_UE | C_AFSR_CE | \
#define C_AFSR_LEVEL1 (C_AFSR_UE | C_AFSR_RUE | C_AFSR_UCU | C_AFSR_EDU | \
#define C_AFSR_ASYNC_ERRS (C_AFSR_UE | C_AFSR_EMU | C_AFSR_EDU | \
C_AFSR_WDU | C_AFSR_EDU | C_AFSR_UE | \
#define C_AFSR_MEMORY (C_AFSR_UE | C_AFSR_CE | C_AFSR_EMU | C_AFSR_EMC | \
#define C_AFSR_ESYND_ERRS (C_AFSR_UE | C_AFSR_CE | \
#define C_AFSR_LEVEL1 (C_AFSR_UE | C_AFSR_UCU | C_AFSR_EMU | C_AFSR_EDU | \
#define C_AFSR_ASYNC_ERRS (C_AFSR_UE | C_AFSR_EMU | C_AFSR_EDU | \
#define C_AFSR_ALL_ME_ERRS (C_AFSR_ISAP | C_AFSR_UE | C_AFSR_IVU | \
#define C_AFSR_MEMORY (C_AFSR_UE | C_AFSR_CE | C_AFSR_EMU | C_AFSR_EMC)
#define C_AFSR_ESYND_ERRS (C_AFSR_UE | C_AFSR_CE | \
#define C_AFSR_LEVEL1 (C_AFSR_UE | C_AFSR_UCU | C_AFSR_EMU | C_AFSR_EDU | \
C_AFSR_UE | C_AFSR_RUE | C_AFSR_EDU | C_AFSR_BP | \
C_AFSR_UE | C_AFSR_RUE | C_AFSR_EDU | C_AFSR_BP)