C_AFSR_UCU
C_AFSR_UCU, "OUCU ", ECC_ORPH_TRAPS, CPU_ORPH,
C_AFSR_UCU, "UCU ", ECC_F_TRAP, CPU_UE_ECACHE,
C_AFSR_UCC | C_AFSR_UCU,
C_AFSR_UE | C_AFSR_IVU | C_AFSR_EDU | C_AFSR_WDU | C_AFSR_UCU |
C_AFSR_UCU, "OUCU ", ECC_ORPH_TRAPS,
C_AFSR_UCU, "UCU ", ECC_F_TRAP,
C_AFSR_UCC | C_AFSR_UCU | C_AFSR_TUE | C_AFSR_TSCE | C_AFSR_TUE_SH |
C_AFSR_WDU | C_AFSR_UCU | C_AFSR_CPU,
C_AFSR_UCU | C_AFSR_UCC |
if ((t_afsr_errs & (C_AFSR_UCU | C_AFSR_L3_UCU)) &&
case C_AFSR_UCU:
C_AFSR_UCU, "OUCU ", ECC_ORPH_TRAPS, CPU_ORPH,
C_AFSR_UCU, "UCU ", ECC_F_TRAP, CPU_UE_ECACHE,
C_AFSR_UCC | C_AFSR_UCU,
C_AFSR_UE | C_AFSR_FRU | C_AFSR_EDU | C_AFSR_WDU | C_AFSR_UCU |
case C_AFSR_UCU:
#define C_AFSR_L2_SERD_FAIL_UE (C_AFSR_UCU | C_AFSR_CPU | C_AFSR_WDU | \
#define C_AFSR_ALL_ME_ERRS (C_AFSR_ISAP | C_AFSR_UE | C_AFSR_UCU | \
#define C_AFSR_ALL_ME_ERRS (C_AFSR_ISAP | C_AFSR_UE | C_AFSR_UCU | \
C_AFSR_UCU | C_AFSR_UCC | C_AFSR_EDU | C_AFSR_EDC | \
#define C_AFSR_LEVEL1 (C_AFSR_UE | C_AFSR_RUE | C_AFSR_UCU | C_AFSR_EDU | \
#define C_AFSR_FECC_ERRS (C_AFSR_UCU | C_AFSR_UCC | C_AFSR_TSCE)
C_AFSR_BERR | C_AFSR_UCC | C_AFSR_UCU | C_AFSR_CPU | \
#define C_AFSR_EC_DATA_ERRS (C_AFSR_UCU | C_AFSR_UCC | C_AFSR_EDU | \
C_AFSR_UCU | C_AFSR_UCC | C_AFSR_EDU | C_AFSR_EDC | \
#define C_AFSR_LEVEL1 (C_AFSR_UE | C_AFSR_UCU | C_AFSR_EMU | C_AFSR_EDU | \
#define C_AFSR_FECC_ERRS (C_AFSR_UCU | C_AFSR_UCC)
C_AFSR_EMU | C_AFSR_UCU | C_AFSR_EDU | C_AFSR_WDU | \
#define C_AFSR_EC_DATA_ERRS (C_AFSR_UCU | C_AFSR_UCC | C_AFSR_EDU | \
C_AFSR_UCU | C_AFSR_UCC | C_AFSR_EDU | C_AFSR_EDC | \
#define C_AFSR_LEVEL1 (C_AFSR_UE | C_AFSR_UCU | C_AFSR_EMU | C_AFSR_EDU | \
#define C_AFSR_FECC_ERRS (C_AFSR_UCU | C_AFSR_UCC | C_AFSR_ETI | \
#define C_AFSR_FECC_ERRS (C_AFSR_UCU | C_AFSR_UCC)