C_AFSR_UCC
C_AFSR_UCC, "OUCC ", ECC_ORPH_TRAPS, CPU_ORPH,
C_AFSR_UCC, "UCC ", ECC_F_TRAP, CPU_CE_ECACHE,
C_AFSR_UCC | C_AFSR_UCU,
C_AFSR_CE | C_AFSR_IVC | C_AFSR_EDC | C_AFSR_WDC | C_AFSR_UCC |
C_AFSR_UCC, "OUCC ", ECC_ORPH_TRAPS,
C_AFSR_UCC, "UCC ", ECC_F_TRAP,
C_AFSR_UCC | C_AFSR_UCU | C_AFSR_TUE | C_AFSR_TSCE | C_AFSR_TUE_SH |
C_AFSR_UCC | C_AFSR_CPC,
C_AFSR_UCU | C_AFSR_UCC |
case C_AFSR_UCC:
C_AFSR_UCC, "OUCC ", ECC_ORPH_TRAPS, CPU_ORPH,
C_AFSR_UCC, "UCC ", ECC_F_TRAP, CPU_CE_ECACHE,
C_AFSR_UCC | C_AFSR_UCU,
C_AFSR_CE | C_AFSR_FRC | C_AFSR_EDC | C_AFSR_WDC | C_AFSR_UCC |
case C_AFSR_UCC:
#define C_AFSR_L2_SERD_FAIL_CE (C_AFSR_UCC | C_AFSR_CPC | C_AFSR_WDC | \
C_AFSR_EDU | C_AFSR_WDU | C_AFSR_CPU | C_AFSR_UCC | \
C_AFSR_EDU | C_AFSR_WDU | C_AFSR_CPU | C_AFSR_UCC | \
C_AFSR_UCU | C_AFSR_UCC | C_AFSR_EDU | C_AFSR_EDC | \
#define C_AFSR_FECC_ERRS (C_AFSR_UCU | C_AFSR_UCC | C_AFSR_TSCE)
C_AFSR_BERR | C_AFSR_UCC | C_AFSR_UCU | C_AFSR_CPU | \
#define C_AFSR_EC_DATA_ERRS (C_AFSR_UCU | C_AFSR_UCC | C_AFSR_EDU | \
C_AFSR_UCU | C_AFSR_UCC | C_AFSR_EDU | C_AFSR_EDC | \
#define C_AFSR_FECC_ERRS (C_AFSR_UCU | C_AFSR_UCC)
C_AFSR_CPU | C_AFSR_UCC | C_AFSR_BERR | C_AFSR_TO)
#define C_AFSR_EC_DATA_ERRS (C_AFSR_UCU | C_AFSR_UCC | C_AFSR_EDU | \
C_AFSR_UCU | C_AFSR_UCC | C_AFSR_EDU | C_AFSR_EDC | \
#define C_AFSR_FECC_ERRS (C_AFSR_UCU | C_AFSR_UCC | C_AFSR_ETI | \
#define C_AFSR_FECC_ERRS (C_AFSR_UCU | C_AFSR_UCC)