C_AFSR_CPC
C_AFSR_CPC, "CPC ", ECC_C_TRAP, CPU_CE_ECACHE,
C_AFSR_CE | C_AFSR_EDC | C_AFSR_EMC | C_AFSR_WDC | C_AFSR_CPC,
C_AFSR_CPC,
C_AFSR_CPC, "CPC ", ECC_C_TRAP,
C_AFSR_CE | C_AFSR_EDC | C_AFSR_EMC | C_AFSR_WDC | C_AFSR_CPC |
C_AFSR_UCC | C_AFSR_CPC,
C_AFSR_CE | C_AFSR_IVC | C_AFSR_EDC | C_AFSR_WDC | C_AFSR_CPC |
if (afsr & (C_AFSR_EDC | C_AFSR_CPC | C_AFSR_CPU | C_AFSR_WDC))
if (afsr_errs & (C_AFSR_EDC | C_AFSR_CPC | C_AFSR_WDC | C_AFSR_L3_EDC |
if (afsr & (C_AFSR_CPC | C_AFSR_CPU | C_AFSR_EDC | C_AFSR_WDC)) {
if (afsr_errs & (C_AFSR_CPC | C_AFSR_EDC | C_AFSR_WDC | C_AFSR_L3_CPC |
case C_AFSR_CPC:
C_AFSR_CPC, "CPC ", ECC_C_TRAP, CPU_CE_ECACHE,
C_AFSR_CPC | C_AFSR_FRC,
C_AFSR_CE | C_AFSR_RCE | C_AFSR_EDC | C_AFSR_WDC | C_AFSR_CPC,
C_AFSR_CPC,
case C_AFSR_CPC:
#define C_AFSR_L2_SERD_FAIL_CE (C_AFSR_UCC | C_AFSR_CPC | C_AFSR_WDC | \
C_AFSR_WDU | C_AFSR_WDC | C_AFSR_CPU | C_AFSR_CPC | \
C_AFSR_CPC | C_AFSR_IVU | C_AFSR_IVC | C_AFSR_DUE | \
C_AFSR_CPC)
C_AFSR_WDU | C_AFSR_WDC | C_AFSR_CPU | C_AFSR_CPC | \
C_AFSR_CPC | C_AFSR_IVU | C_AFSR_IVC)
C_AFSR_CPC)
C_AFSR_WDU | C_AFSR_WDC | C_AFSR_CPU | C_AFSR_CPC | \
#define C_AFSR_AID_ERRS (C_AFSR_CPU | C_AFSR_FRU | C_AFSR_CPC | \
#define C_AFSR_CECC_ERRS (C_AFSR_UMS | C_AFSR_IVPE | C_AFSR_CPC | \
#define C_AFSR_CECC_ERRS (C_AFSR_UMS | C_AFSR_IVPE | C_AFSR_CPC | \