gmac
param->gmac = iv; /* see above */
CK_AES_GMAC_PARAMS gmac;
param->gmac.pIv = iv;
param->gmac.pAAD = NULL;
param->gmac.ulAADLen = 0;
mech->cm_param = (caddr_t)¶m->gmac;
mech->cm_param_len = sizeof (param->gmac);
struct gmac t1_chelsio_mac_ops = {
adapter->params.stats_update_period = bi->gmac->stats_update_period;
if (bi->gmac->reset)
bi->gmac->reset(adapter);
adapter->port[i].mac = mac = bi->gmac->create(adapter, i);
struct gmac;
struct gmac *gmac;
extern struct gmac t1_pm3393_ops;
extern struct gmac t1_chelsio_mac_ops;
extern struct gmac t1_vsc7321_ops;
extern struct gmac t1_vsc7326_ops;
extern struct gmac t1_ixf1010_ops;
extern struct gmac t1_dummy_mac_ops;
struct gmac t1_ixf1010_ops = {
struct gmac t1_pm3393_ops = {
struct gmac t1_vsc7321_ops = {
struct gmac t1_vsc7326_ops = {
uint16_t gmac;
gmac = DATA_BLIND_VAL(DATA_BLIND_DEF) |
gmac |= GM_SMOD_JUMBO_ENA;
GMAC_WRITE_2(dev, pnum, GM_SERIAL_MODE, gmac);
gmac = GMAC_READ_2(dev, pnum, GM_GP_CTRL);
gmac |= (GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
GMAC_WRITE_2(port->p_dev, port->p_port, GM_GP_CTRL, gmac);
uint16_t gmac;
gmac = GMAC_READ_2(dev, pnum, GM_PHY_ADDR);
GMAC_WRITE_2(dev, pnum, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR);
gmac &= ~GM_PAR_MIB_CLR;
GMAC_WRITE_2(dev, pnum, GM_PHY_ADDR, gmac);
uint16_t gmac;
gmac = GMAC_READ_2(dev, pnum, GM_PHY_ADDR);
GMAC_WRITE_2(dev, pnum, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR);
gmac &= ~GM_PAR_MIB_CLR;
GMAC_WRITE_2(dev, pnum, GM_PHY_ADDR, gmac);
uint32_t gmac;
gmac = GMC_PAUSE_ON;
gmac = GMC_PAUSE_ON;
gmac = GMC_PAUSE_ON;
gmac = GMC_PAUSE_OFF;
gmac = GMC_PAUSE_OFF;
CSR_WRITE_4(dev, MR_ADDR(port->p_port, GMAC_CTRL), gmac);
CK_AES_GMAC_PARAMS gmac;
CK_BYTE_PTR gmac; /* Just IV[12] */