fnvlist_add_uint32
fnvlist_add_uint32(t, "itr_sock_gran", r->itr_sock_gran);
fnvlist_add_uint32(t, "itr_chan_gran", r->itr_chan_gran);
fnvlist_add_uint32(nvl, "ich_valid", chan->ich_valid);
fnvlist_add_uint32(d, "idimm_valid", dimm->idimm_valid);
fnvlist_add_uint32(nvl, "icn_dimm_type", mc->icn_dimm_type);
fnvlist_add_uint32(nvl, "isock_nodeid", sock->isock_nodeid);
fnvlist_add_uint32(nvl, "mc_dump_version", 0);
fnvlist_add_uint32(invl, "imc_gen", imc->imc_gen);
fnvlist_add_uint32(nvl, "isad_flags", sad->isad_flags);
fnvlist_add_uint32(nvl, "isad_valid", sad->isad_valid);
fnvlist_add_uint32(n, "isr_type", r->isr_type);
fnvlist_add_uint32(n, "isr_imode", r->isr_imode);
fnvlist_add_uint32(n, "isr_mod_mode", r->isr_mod_mode);
fnvlist_add_uint32(n, "isr_mod_type", r->isr_mod_type);
fnvlist_add_uint32(nvl, "itad_valid", tad->itad_valid);
fnvlist_add_uint32(nvl, "itad_flags", tad->itad_flags);
fnvlist_add_uint32(nvl, "ud_width", dimm->ud_width);
fnvlist_add_uint32(nvl, "ud_kind", dimm->ud_kind);
fnvlist_add_uint32(nvl, "ud_dimmno", dimm->ud_dimmno);
fnvlist_add_uint32(nvl, "uch_flags", hash->uch_flags);
fnvlist_add_uint32(banks[i], "ubh_row_xor",
fnvlist_add_uint32(banks[i], "ubh_col_xor",
fnvlist_add_uint32(pc, "uph_row_xor",
fnvlist_add_uint32(pc, "uph_col_xor",
fnvlist_add_uint32(nvl, "chan_flags", chan->chan_flags);
fnvlist_add_uint32(nvl, "chan_fabid", chan->chan_fabid);
fnvlist_add_uint32(nvl, "chan_instid", chan->chan_instid);
fnvlist_add_uint32(nvl, "chan_logid", chan->chan_logid);
fnvlist_add_uint32(nvl, "chan_np2_space0", chan->chan_np2_space0);
fnvlist_add_uint32(nvl, "chan_type", chan->chan_type);
fnvlist_add_uint32(nvl, "zud_flags", df->zud_flags);
fnvlist_add_uint32(nvl, "zud_dfno", df->zud_dfno);
fnvlist_add_uint32(nvl, "zud_ccm_inst", df->zud_ccm_inst);
fnvlist_add_uint32(nvl, "mc_dump_version", 0);
fnvlist_add_uint32(umc_nvl, "umc_family", umc->umc_family);
fnvlist_add_uint32(umc_nvl, "umc_df_rev", umc->umc_df_rev);
fnvlist_add_uint32(decomp, "dfd_sock_mask",
fnvlist_add_uint32(decomp, "dfd_die_mask",
fnvlist_add_uint32(decomp, "dfd_node_mask",
fnvlist_add_uint32(decomp, "dfd_comp_mask",
fnvlist_add_uint32(nvl, "ddr_flags", rule->ddr_flags);
fnvlist_add_uint32(nvl, "ddr_chan_ileave", rule->ddr_chan_ileave);
fnvlist_add_uint32(nvl, "ucs_flags", cs->ucs_flags);
fnvlist_add_uint32(nvl, "ud_flags", dimm->ud_flags);
fnvlist_add_uint32(nvl, "tx_copy_data", 0);
fnvlist_add_uint32(nvl, UI2C_IOCTL_NVL_ADDR, 0x00);
fnvlist_add_uint32(nvl, GPIO_SIM_ATTR_INPUT, GPIO_SIM_INPUT_LOW);
fnvlist_add_uint32(nvl, GPIO_SIM_ATTR_VOLTAGE, GPIO_SIM_VOLTAGE_54P5);
fnvlist_add_uint32(nvl, "calvinball", 0x23);
fnvlist_add_uint32(nvl, "calvinball", 0x23);
fnvlist_add_uint32(nvl, GPIO_SIM_ATTR_SPEED, GPIO_SIM_SPEED_MEDIUM);
fnvlist_add_uint32(nested, GPIO_SIM_ATTR_PULL, 1);
fnvlist_add_uint32(nested, GPIO_SIM_ATTR_OUTPUT, 2);
fnvlist_add_uint32(nvl, GPIO_SIM_ATTR_OUTPUT, 0x42);
fnvlist_add_uint32(nvl, GPIO_SIM_ATTR_PULL, UINT32_MAX);
fnvlist_add_uint32(nvl, GPIO_SIM_ATTR_SPEED,
fnvlist_add_uint32(nvl, GPIO_SIM_ATTR_OUTPUT, GPIO_SIM_OUTPUT_HIGH);
fnvlist_add_uint32(nvl, GPIO_SIM_ATTR_PULL, GPIO_SIM_PULL_UP_5K);
fnvlist_add_uint32(nvl, GPIO_SIM_ATTR_OUTPUT, GPIO_SIM_OUTPUT_HIGH);
fnvlist_add_uint32(nvl, GPIO_SIM_ATTR_VOLTAGE, GPIO_SIM_VOLTAGE_54P5);
fnvlist_add_uint32(nvl, "triforce", 0x23);
fnvlist_add_uint32(nvl, GPIO_SIM_ATTR_SPEED, 0xbadcafe);
fnvlist_add_uint32(payload, "mss", popts->po_mss);
fnvlist_add_uint32(payload, "padding", popts->po_padding);
fnvlist_add_uint32(payload, "offset", offset);
fnvlist_add_uint32(payload, "tci", tci);
fnvlist_add_uint32(nvl, key, 1);
fnvlist_add_uint32(errs, nvpair_name(nvpair),
fnvlist_add_uint32(errs, nvpair_name(nvpair),
fnvlist_add_uint32(errs, nvpair_name(nvpair),
fnvlist_add_uint32(errs, nvpair_name(nvpair),
fnvlist_add_uint32(errs, nvpair_name(nvpair),
fnvlist_add_uint32(errs, nvpair_name(nvpair),
fnvlist_add_uint32(errs, nvpair_name(nvpair),
fnvlist_add_uint32(errs, nvpair_name(nvpair),
fnvlist_add_uint32(errs, nvpair_name(nvpair),
fnvlist_add_uint32(errs, nvpair_name(nvpair),
fnvlist_add_uint32(errs, name,
fnvlist_add_uint32(info, KGPIO_ATTR_PROT, (uint32_t)prot);
fnvlist_add_uint32(nvl, key, val);
fnvlist_add_uint32(info, KGPIO_ATTR_PROT, (uint32_t)prot);
fnvlist_add_uint32(errs, name, (uint32_t)KGPIO_ATTR_ERR_ATTR_RO);
fnvlist_add_uint32(errs, nvpair_name(pair),
fnvlist_add_uint32(errs, nvpair_name(pair),
fnvlist_add_uint32(errs, nvpair_name(pair),
fnvlist_add_uint32(errs, nvpair_name(pair),
fnvlist_add_uint32(errs, name, (uint32_t)KGPIO_ATTR_ERR_ATTR_RO);
fnvlist_add_uint32(errs, nvpair_name(pair),
fnvlist_add_uint32(errs, nvpair_name(pair),
fnvlist_add_uint32(errs, nvpair_name(pair),
fnvlist_add_uint32(errs, nvpair_name(pair),
fnvlist_add_uint32(slots[s], DDI_UFM_NV_SLOT_ATTR,
void fnvlist_add_uint32(nvlist_t *, const char *, uint32_t);
fnvlist_add_uint32(caches[i], FM_CACHE_INFO_LEVEL, c.xc_level);
fnvlist_add_uint32(caches[i], FM_CACHE_INFO_TYPE,
fnvlist_add_uint32(caches[i], FM_CACHE_INFO_NWAYS, c.xc_nways);
fnvlist_add_uint32(caches[i], FM_CACHE_INFO_LINE_SIZE,
fnvlist_add_uint32(caches[i], FM_CACHE_INFO_X86_APIC_SHIFT,
fnvlist_add_uint32(nvl, FM_CACHE_INFO_NCPUS, walk.nhdl);
fnvlist_add_uint32(nvl, MCINTEL_NVLIST_V1_DIMM_NCOLS,
fnvlist_add_uint32(nvl, MCINTEL_NVLIST_V1_DIMM_NROWS,
fnvlist_add_uint32(nvl, MCINTEL_NVLIST_V1_DIMM_WIDTH,
fnvlist_add_uint32(nvl, MCINTEL_NVLIST_V1_DIMM_RANKS,
fnvlist_add_uint32(nvl, MCINTEL_NVLIST_V1_DIMM_BANKS,
fnvlist_add_uint32(nvl, MCINTEL_NVLIST_V1_DIMM_3DRANK,
fnvlist_add_uint32(nvl, MCINTEL_NVLIST_V1_CHAN_NDPC,
fnvlist_add_uint32(nvl, MCINTEL_NVLIST_V1_MC_NCHAN, icn->icn_nchannels);