CSR_WRITE_4
CSR_WRITE_4(pcnp, PCN_IO32_RDP, 0);
CSR_WRITE_4(pcnp, PCN_IO32_RAP, reg);
CSR_WRITE_4(pcnp, PCN_IO32_RAP, reg);
CSR_WRITE_4(pcnp, PCN_IO32_RDP, val);
CSR_WRITE_4(pcnp, PCN_IO32_RAP, reg);
CSR_WRITE_4(pcnp, PCN_IO32_RAP, reg);
CSR_WRITE_4(pcnp, PCN_IO32_BDP, val);
CSR_WRITE_4(pcnp, PCN_IO32_RAP, PCN_CSR_EXTCTL1);
CSR_WRITE_4(pcnp, PCN_IO32_RDP, CSR_READ_4(pcnp, PCN_IO32_RDP) &
CSR_WRITE_4(pcnp, PCN_IO32_RAP, PCN_CSR_CSR);
CSR_WRITE_4(pcnp, PCN_IO32_RDP,
CSR_WRITE_4(dev, B0_IMSK, 0);
CSR_WRITE_4(dev, B0_HWE_IMSK, 0);
CSR_WRITE_4(dev, B0_IMSK, 0);
CSR_WRITE_4(dev, B0_HWE_IMSK, 0);
CSR_WRITE_4(dev, B0_IMSK, 0);
CSR_WRITE_4(dev, B0_IMSK, Y2_IS_HW_ERR | Y2_IS_STAT_BMU);
CSR_WRITE_4(dev, B0_HWE_IMSK,
CSR_WRITE_4(dev, MR_ADDR(pnum, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
CSR_WRITE_4(dev, MR_ADDR(port->p_port, TX_GMF_CTRL_T),
CSR_WRITE_4(dev, Q_ADDR(port->p_rxq, Q_CSR), BMU_CLR_IRQ_PAR);
CSR_WRITE_4(dev, Q_ADDR(port->p_txq, Q_CSR), BMU_CLR_IRQ_TCP);
CSR_WRITE_4(dev, B0_HWE_IMSK,
CSR_WRITE_4(dev, B0_Y2_SP_ICR, 2);
CSR_WRITE_4(dev, B0_IMSK, dev->d_intrmask);
CSR_WRITE_4(dev, B0_IMSK, dev->d_intrmask);
CSR_WRITE_4(dev, STAT_CTRL, SC_STAT_CLR_IRQ);
CSR_WRITE_4(dev, B0_Y2_SP_ICR, 2);
CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T),
CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T),
CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_AE_THR),
CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T),
CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T),
CSR_WRITE_4(dev, MR_ADDR(pnum, GMAC_CTRL), GMC_RST_SET);
CSR_WRITE_4(dev, MR_ADDR(pnum, GMAC_CTRL), GMC_RST_CLR);
CSR_WRITE_4(dev, MR_ADDR(pnum, GMAC_CTRL), GMC_F_LOOPB_OFF);
CSR_WRITE_4(dev, MR_ADDR(pnum, GMAC_CTRL),
CSR_WRITE_4(dev, MR_ADDR(pnum, RX_GMF_CTRL_T), GMF_RST_SET);
CSR_WRITE_4(dev, MR_ADDR(pnum, RX_GMF_CTRL_T), GMF_RST_CLR);
CSR_WRITE_4(dev, MR_ADDR(pnum, RX_GMF_CTRL_T), reg);
CSR_WRITE_4(dev, MR_ADDR(pnum, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
CSR_WRITE_4(dev, MR_ADDR(pnum, RX_GMF_FL_THR), reg);
CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T), GMF_RST_SET);
CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T), GMF_RST_CLR);
CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T), GMF_OPER_ON);
CSR_WRITE_4(dev, MR_ADDR(pnum, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_EA), reg);
CSR_WRITE_4(dev, Q_ADDR(txq, Q_CSR), BMU_CLR_RESET);
CSR_WRITE_4(dev, Q_ADDR(txq, Q_CSR), BMU_OPER_INIT);
CSR_WRITE_4(dev, Q_ADDR(txq, Q_CSR), BMU_FIFO_OP_ON);
CSR_WRITE_4(dev, Q_ADDR(txq, Q_F), F_TX_CHK_AUTO_OFF);
CSR_WRITE_4(dev, Q_ADDR(rxq, Q_CSR), BMU_CLR_RESET);
CSR_WRITE_4(dev, Q_ADDR(rxq, Q_CSR), BMU_OPER_INIT);
CSR_WRITE_4(dev, Q_ADDR(rxq, Q_CSR), BMU_FIFO_OP_ON);
CSR_WRITE_4(dev, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
CSR_WRITE_4(dev, Q_ADDR(rxq, Q_CSR),
CSR_WRITE_4(dev, B0_HWE_IMSK, dev->d_intrhwemask);
CSR_WRITE_4(dev, B0_IMSK, dev->d_intrmask);
CSR_WRITE_4(dev, RB_ADDR(rxq, RB_START), dev->d_rxqstart[pnum] / 8);
CSR_WRITE_4(dev, RB_ADDR(rxq, RB_END), dev->d_rxqend[pnum] / 8);
CSR_WRITE_4(dev, RB_ADDR(rxq, RB_WP), dev->d_rxqstart[pnum] / 8);
CSR_WRITE_4(dev, RB_ADDR(rxq, RB_RP), dev->d_rxqstart[pnum] / 8);
CSR_WRITE_4(dev, RB_ADDR(rxq, RB_RX_UTPP), utpp);
CSR_WRITE_4(dev, RB_ADDR(rxq, RB_RX_LTPP), ltpp);
CSR_WRITE_4(dev, RB_ADDR(txq, RB_START), dev->d_txqstart[pnum] / 8);
CSR_WRITE_4(dev, RB_ADDR(txq, RB_END), dev->d_txqend[pnum] / 8);
CSR_WRITE_4(dev, RB_ADDR(txq, RB_WP), dev->d_txqstart[pnum] / 8);
CSR_WRITE_4(dev, RB_ADDR(txq, RB_RP), dev->d_txqstart[pnum] / 8);
CSR_WRITE_4(dev, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG),
CSR_WRITE_4(dev, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG),
CSR_WRITE_4(dev, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_LOW_REG),
CSR_WRITE_4(dev, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_HI_REG),
CSR_WRITE_4(dev, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG),
CSR_WRITE_4(dev, B0_HWE_IMSK, dev->d_intrhwemask);
CSR_WRITE_4(dev, B0_IMSK, dev->d_intrmask);
CSR_WRITE_4(dev, Q_ADDR(txq, Q_CSR), BMU_STOP);
CSR_WRITE_4(dev, Q_ADDR(txq, Q_CSR), BMU_STOP);
CSR_WRITE_4(dev, Q_ADDR(txq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
CSR_WRITE_4(dev, Y2_PREF_Q_ADDR(txq, PREF_UNIT_CTRL_REG),
CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T), GMF_RST_SET);
CSR_WRITE_4(dev, MR_ADDR(pnum, GMAC_CTRL), GMC_PAUSE_OFF);
CSR_WRITE_4(dev, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
CSR_WRITE_4(dev, Y2_PREF_Q_ADDR(rxq, PREF_UNIT_CTRL_REG),
CSR_WRITE_4(dev, MR_ADDR(pnum, RX_GMF_CTRL_T), GMF_RST_SET);
CSR_WRITE_4(dev, B0_IMSK, 0);
CSR_WRITE_4(dev, B0_HWE_IMSK, 0);
CSR_WRITE_4(dev, MR_ADDR(port->p_port, GMAC_CTRL), gmac);
CSR_WRITE_4(dev, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
CSR_WRITE_4(dev, B2_GP_IO, our);
CSR_WRITE_4(dev, MR_ADDR(i, GPHY_CTRL), GPC_RST_SET);
CSR_WRITE_4(dev, MR_ADDR(i, GPHY_CTRL), GPC_RST_CLR);
CSR_WRITE_4(dev, MR_ADDR(i, GMAC_CTRL), GMC_RST_SET);
CSR_WRITE_4(dev, MR_ADDR(i, GMAC_CTRL), GMC_RST_CLR);
CSR_WRITE_4(dev, B2_I2C_IRQ, I2C_CLR_IRQ);
CSR_WRITE_4(dev, B0_HWE_IMSK, 0);
CSR_WRITE_4(dev, B0_IMSK, 0);
CSR_WRITE_4(dev, STAT_CTRL, SC_STAT_RST_SET);
CSR_WRITE_4(dev, STAT_CTRL, SC_STAT_RST_CLR);
CSR_WRITE_4(dev, STAT_LIST_ADDR_LO, YGE_ADDR_LO(addr));
CSR_WRITE_4(dev, STAT_LIST_ADDR_HI, YGE_ADDR_HI(addr));
CSR_WRITE_4(dev, STAT_ISR_TIMER_INI, 0x0190);
CSR_WRITE_4(dev, STAT_TX_TIMER_INI, YGE_USECS(dev, 1000));
CSR_WRITE_4(dev, STAT_CTRL, SC_STAT_OP_ON);
#define CSR_PCI_WRITE_4(d, reg, v) CSR_WRITE_4(d, Y2_CFG_SPC + (reg), (v))