CSR_WRITE_2
CSR_WRITE_2(pcnp, PCN_IO16_RAP, reg);
CSR_WRITE_2(pcnp, PCN_IO16_RAP, reg);
CSR_WRITE_2(dev, B0_CTST, CS_RST_CLR);
CSR_WRITE_2(dev, B0_CTST, CS_RST_SET);
CSR_WRITE_2(dev, B0_CTST, CS_RST_CLR);
CSR_WRITE_2(dev, B0_CTST, Y2_LED_STAT_OFF);
CSR_WRITE_2(dev, B0_CTST, CS_RST_SET);
CSR_WRITE_2(dev, B0_CTST, CS_RST_SET);
CSR_WRITE_2(dev,
CSR_WRITE_2(dev, SELECT_RAM_BUFFER(port->p_port, B3_RI_CTRL),
CSR_WRITE_2(dev, SELECT_RAM_BUFFER(port->p_port, B3_RI_CTRL),
CSR_WRITE_2(dev, Q_ADDR(txq, Q_WM), MSK_BMU_TX_WM);
CSR_WRITE_2(dev, Q_ADDR(txq, Q_AL), MSK_ECU_TXFF_LEV);
CSR_WRITE_2(dev, Q_ADDR(rxq, Q_WM), 0x80);
CSR_WRITE_2(dev, Q_ADDR(rxq, Q_WM), MSK_BMU_RX_WM);
CSR_WRITE_2(dev, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_LAST_IDX_REG),
CSR_WRITE_2(port->p_dev,
CSR_WRITE_2(dev, B0_CTST, CS_RST_SET);
CSR_WRITE_2(port->p_dev,
CSR_WRITE_2(dev, B0_CTST, Y2_HW_WOL_OFF);
CSR_WRITE_2(dev, MR_ADDR(i, GMAC_LINK_CTRL),
CSR_WRITE_2(dev, MR_ADDR(i, GMAC_LINK_CTRL),
CSR_WRITE_2(dev, B28_Y2_ASF_STAT_CMD, status);
CSR_WRITE_2(dev, B0_CTST, Y2_ASF_DISABLE);
CSR_WRITE_2(dev, MR_ADDR(i, GMAC_CTRL),
CSR_WRITE_2(dev, MR_ADDR(i, GMAC_CTRL), GMC_F_LOOPB_OFF);
CSR_WRITE_2(dev, B0_CTST, Y2_LED_STAT_ON);
CSR_WRITE_2(dev, STAT_LAST_IDX, YGE_STAT_RING_CNT - 1);
CSR_WRITE_2(dev, STAT_PUT_IDX, 0);
CSR_WRITE_2(dev, STAT_TX_IDX_TH, ST_TXTH_IDX_MASK);
CSR_WRITE_2(dev, STAT_TX_IDX_TH, 10);
#define CSR_PCI_WRITE_2(d, reg, v) CSR_WRITE_2(d, Y2_CFG_SPC + (reg), (v))
CSR_WRITE_2((sc), GMAC_REG((port), (reg)), (val))