CSR_WRITE_1
CSR_WRITE_1(dev, B2_TST_CTRL1, TST_CFG_WRITE_ON);
CSR_WRITE_1(dev, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
CSR_WRITE_1(dev, B2_TST_CTRL1, TST_CFG_WRITE_ON);
CSR_WRITE_1(dev, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
CSR_WRITE_1(dev, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
CSR_WRITE_1(dev, B2_TST_CTRL1, TST_CFG_WRITE_ON);
CSR_WRITE_1(dev, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
CSR_WRITE_1(dev, B2_TST_CTRL1, TST_CFG_WRITE_ON);
CSR_WRITE_1(dev, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
CSR_WRITE_1(dev, MR_ADDR(pnum, RX_GMF_LP_THR),
CSR_WRITE_1(dev, MR_ADDR(pnum, RX_GMF_UP_THR),
CSR_WRITE_1(dev, MR_ADDR(pnum, RX_GMF_LP_THR),
CSR_WRITE_1(dev, MR_ADDR(pnum, RX_GMF_UP_THR),
CSR_WRITE_1(dev, MR_ADDR(pnum, TXA_CTRL),
CSR_WRITE_1(dev, MR_ADDR(pnum, TXA_CTRL), TXA_ENA_ARB);
CSR_WRITE_1(dev, RB_ADDR(port->p_txsq, RB_CTRL), RB_RST_SET);
CSR_WRITE_1(dev, RB_ADDR(rxq, RB_CTRL), RB_RST_CLR);
CSR_WRITE_1(dev, RB_ADDR(rxq, RB_CTRL), RB_ENA_OP_MD);
CSR_WRITE_1(dev, RB_ADDR(txq, RB_CTRL), RB_RST_CLR);
CSR_WRITE_1(dev, RB_ADDR(txq, RB_CTRL), RB_ENA_STFWD);
CSR_WRITE_1(dev, RB_ADDR(txq, RB_CTRL), RB_ENA_OP_MD);
CSR_WRITE_1(dev, RB_ADDR(txq, RB_CTRL), RB_RST_SET | RB_DIS_OP_MD);
CSR_WRITE_1(dev, MR_ADDR(pnum, GMAC_IRQ_MSK), 0);
CSR_WRITE_1(dev, MR_ADDR(pnum, TXA_CTRL), TXA_DIS_ARB);
CSR_WRITE_1(dev, RB_ADDR(txq, RB_CTRL), RB_RST_SET);
CSR_WRITE_1(dev, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
CSR_WRITE_1(dev, RB_ADDR(rxq, RB_CTRL), RB_RST_SET);
CSR_WRITE_1(dev, MR_ADDR(port->p_port, GMAC_IRQ_MSK),
CSR_WRITE_1(dev, B0_POWER_CTRL,
CSR_WRITE_1(dev, B2_Y2_CLK_GATE, val);
CSR_WRITE_1(dev, B2_Y2_CLK_GATE, val);
CSR_WRITE_1(dev, B0_POWER_CTRL,
CSR_WRITE_1(dev, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
CSR_WRITE_1(dev, B0_CTST, CS_RST_SET);
CSR_WRITE_1(dev, B0_CTST, CS_RST_CLR);
CSR_WRITE_1(dev, B2_TST_CTRL1, TST_CFG_WRITE_ON);
CSR_WRITE_1(dev, B2_TST_CTRL1, TST_CFG_WRITE_ON);
CSR_WRITE_1(dev, B0_CTST, CS_MRST_CLR);
CSR_WRITE_1(dev, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
CSR_WRITE_1(dev, B2_TI_CTRL, TIM_STOP);
CSR_WRITE_1(dev, B2_TI_CTRL, TIM_CLR_IRQ);
CSR_WRITE_1(dev, B28_DPT_CTRL, DPT_STOP);
CSR_WRITE_1(dev, GMAC_TI_ST_CTRL, GMT_ST_STOP);
CSR_WRITE_1(dev, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
CSR_WRITE_1(dev, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
CSR_WRITE_1(dev, MR_ADDR(i, TXA_CTRL), TXA_ENA_ARB);
CSR_WRITE_1(dev, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
CSR_WRITE_1(dev, SELECT_RAM_BUFFER(i, B3_RI_WTO_R1), RI_TO_53);
CSR_WRITE_1(dev, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA1), RI_TO_53);
CSR_WRITE_1(dev, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS1), RI_TO_53);
CSR_WRITE_1(dev, SELECT_RAM_BUFFER(i, B3_RI_RTO_R1), RI_TO_53);
CSR_WRITE_1(dev, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA1), RI_TO_53);
CSR_WRITE_1(dev, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS1), RI_TO_53);
CSR_WRITE_1(dev, SELECT_RAM_BUFFER(i, B3_RI_WTO_R2), RI_TO_53);
CSR_WRITE_1(dev, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA2), RI_TO_53);
CSR_WRITE_1(dev, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS2), RI_TO_53);
CSR_WRITE_1(dev, SELECT_RAM_BUFFER(i, B3_RI_RTO_R2), RI_TO_53);
CSR_WRITE_1(dev, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA2), RI_TO_53);
CSR_WRITE_1(dev, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS2), RI_TO_53);
CSR_WRITE_1(dev, B2_TST_CTRL1, TST_CFG_WRITE_ON);
CSR_WRITE_1(dev, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
CSR_WRITE_1(dev, STAT_FIFO_WM, 0x21);
CSR_WRITE_1(dev, STAT_FIFO_ISR_WM, 7);
CSR_WRITE_1(dev, STAT_FIFO_WM, 16);
CSR_WRITE_1(dev, STAT_FIFO_ISR_WM, 4);
CSR_WRITE_1(dev, STAT_FIFO_ISR_WM, 16);
CSR_WRITE_1(dev, STAT_TX_TIMER_CTRL, TIM_START);
CSR_WRITE_1(dev, STAT_LEV_TIMER_CTRL, TIM_START);
CSR_WRITE_1(dev, STAT_ISR_TIMER_CTRL, TIM_START);
#define CSR_PCI_WRITE_1(d, reg, v) CSR_WRITE_1(d, Y2_CFG_SPC + (reg), (v))