CSR_READ_4
(void) CSR_READ_4(pcnp, PCN_IO32_RESET);
addr[0] = CSR_READ_4(pcnp, PCN_IO32_APROM00);
addr[1] = CSR_READ_4(pcnp, PCN_IO32_APROM01);
val = CSR_READ_4(pcnp, PCN_IO32_RDP);
val = CSR_READ_4(pcnp, PCN_IO32_BDP);
CSR_WRITE_4(pcnp, PCN_IO32_RDP, CSR_READ_4(pcnp, PCN_IO32_RDP) &
(CSR_READ_4(pcnp, PCN_IO32_RDP) & ~(PCN_CSR_INTEN)) |
(void) CSR_READ_4(dev, B0_IMSK);
(void) CSR_READ_4(dev, B0_HWE_IMSK);
(void) CSR_READ_4(dev, B0_IMSK);
(void) CSR_READ_4(dev, B0_HWE_IMSK);
status = CSR_READ_4(dev, B0_HWE_ISRC);
(void) CSR_READ_4(dev, B0_HWE_IMSK);
status = CSR_READ_4(dev, B0_Y2_SP_ISRC2);
(void) CSR_READ_4(dev, B0_IMSK);
(void) CSR_READ_4(dev, B0_IMSK);
reg = CSR_READ_4(dev, MR_ADDR(pnum, TX_GMF_EA));
(void) CSR_READ_4(dev, B0_HWE_IMSK);
(void) CSR_READ_4(dev, B0_IMSK);
(void) CSR_READ_4(dev, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG));
(void) CSR_READ_4(dev, B0_HWE_IMSK);
(void) CSR_READ_4(dev, B0_IMSK);
val = CSR_READ_4(dev, Q_ADDR(txq, Q_CSR));
val = CSR_READ_4(dev, Q_ADDR(txq, Q_CSR));
(void) CSR_READ_4(dev, B0_IMSK);
(void) CSR_READ_4(dev, B0_HWE_IMSK);
our = CSR_READ_4(dev, B2_GP_IO);
(void) CSR_READ_4(dev, B2_GP_IO);
(void) CSR_READ_4(dev, B0_HWE_IMSK);
(void) CSR_READ_4(dev, B0_IMSK);
#define CSR_PCI_READ_4(d, reg) CSR_READ_4(d, Y2_CFG_SPC + (reg))
CSR_READ_4((sc), GMAC_REG((port), (reg)))