usr/src/uts/common/io/yge/yge.c

1226

dev->d_hw_id = CSR_READ_1(dev, B2_CHIP_ID);

usr/src/uts/common/io/yge/yge.c

1227

dev->d_hw_rev = (CSR_READ_1(dev, B2_MAC_CFG) >> 4) & 0x0f;

usr/src/uts/common/io/yge/yge.c

1248

dev->d_pmd = CSR_READ_1(dev, B2_PMD_TYP);

usr/src/uts/common/io/yge/yge.c

1255

if ((CSR_READ_1(dev, B2_Y2_HW_RES) & CFG_DUAL_MAC_MSK) ==

usr/src/uts/common/io/yge/yge.c

1257

if (!(CSR_READ_1(dev, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))

usr/src/uts/common/io/yge/yge.c

2027

status = CSR_READ_1(dev, MR_ADDR(pnum, GMAC_IRQ_SRC));

usr/src/uts/common/io/yge/yge.c

2452

(void) CSR_READ_1(dev, MR_ADDR(pnum, GMAC_IRQ_SRC));

usr/src/uts/common/io/yge/yge.c

2667

(void) CSR_READ_1(dev, RB_ADDR(rxq, RB_CTRL));

usr/src/uts/common/io/yge/yge.c

2678

(void) CSR_READ_1(dev, RB_ADDR(txq, RB_CTRL));

usr/src/uts/common/io/yge/yge.c

2796

if (CSR_READ_1(dev, RB_ADDR(rxq, Q_RSL)) ==

usr/src/uts/common/io/yge/yge.c

2797

CSR_READ_1(dev, RB_ADDR(rxq, Q_RL)))

usr/src/uts/common/io/yge/yge.c

542

dev->d_ramsize = CSR_READ_1(dev, B2_E_0) * 4;

usr/src/uts/common/io/yge/yge.c

966

CSR_READ_1(dev, B2_MAC_1 + (port->p_port * 8) + i);

usr/src/uts/common/io/yge/yge.h

1836

#define CSR_PCI_READ_1(d, reg) CSR_READ_1(d, Y2_CFG_SPC + (reg))