emu10k_write_reg
emu10k_write_reg(devc, VEDS, voice, 0x0);
emu10k_write_reg(devc, IP, voice, 0x0);
emu10k_write_reg(devc, VTFT, voice, 0xffff);
emu10k_write_reg(devc, CVCF, voice, 0xffff);
emu10k_write_reg(devc, PTAB, voice, 0x0);
emu10k_write_reg(devc, CPF, voice, 0x0);
emu10k_write_reg(devc, CCR, voice, 0x0);
emu10k_write_reg(devc, SCSA, voice, 0x0);
emu10k_write_reg(devc, SDL, voice, 0x10);
emu10k_write_reg(devc, QKBCA, voice, 0x0);
emu10k_write_reg(devc, Z1, voice, 0x0);
emu10k_write_reg(devc, Z2, voice, 0x0);
emu10k_write_reg(devc, SRDA, voice, 0x03020100);
emu10k_write_reg(devc, FXRT, voice, 0x32100000);
emu10k_write_reg(devc, MEHA, voice, 0x0);
emu10k_write_reg(devc, MEDS, voice, 0x0);
emu10k_write_reg(devc, IFA, voice, 0xffff);
emu10k_write_reg(devc, PEFE, voice, 0x0);
emu10k_write_reg(devc, VFM, voice, 0x0);
emu10k_write_reg(devc, TMFQ, voice, 24);
emu10k_write_reg(devc, VVFQ, voice, 24);
emu10k_write_reg(devc, TMPE, voice, 0x0);
emu10k_write_reg(devc, VLV, voice, 0x0);
emu10k_write_reg(devc, MLV, voice, 0x0);
emu10k_write_reg(devc, VEHA, voice, 0x0);
emu10k_write_reg(devc, VEV, voice, 0x0);
emu10k_write_reg(devc, MEV, voice, 0x0);
emu10k_write_reg(devc, CSBA, voice, 0x0);
emu10k_write_reg(devc, CSDC, voice, 0x0);
emu10k_write_reg(devc, CSFE, voice, 0x0);
emu10k_write_reg(devc, CSHG, voice, 0x0);
emu10k_write_reg(devc, SRHE, voice, 0x3f3f3f3f);
emu10k_write_reg(devc, AC97SLOT, 0, AC97SLOT_CENTER | AC97SLOT_LFE);
emu10k_write_reg(devc, MBS, 0, 0x0);
emu10k_write_reg(devc, MBA, 0, 0x0);
emu10k_write_reg(devc, FXBS, 0, 0x0);
emu10k_write_reg(devc, FXBA, 0, 0x0);
emu10k_write_reg(devc, ADCBS, 0, 0x0);
emu10k_write_reg(devc, ADCBA, 0, 0x0);
emu10k_write_reg(devc, CLIEL, 0, 0x0);
emu10k_write_reg(devc, CLIEH, 0, 0x0);
emu10k_write_reg(devc, HLIEL, 0, 0x0);
emu10k_write_reg(devc, HLIEH, 0, 0x0);
emu10k_write_reg(devc, CLIPL, 0, 0xffffffff);
emu10k_write_reg(devc, CLIPH, 0, 0xffffffff);
emu10k_write_reg(devc, SOLL, 0, 0xffffffff);
emu10k_write_reg(devc, SOLH, 0, 0xffffffff);
emu10k_write_reg(devc, SOC, 0, 0xf00); /* ?? */
emu10k_write_reg(devc, AC97SLOT, 0, 0x3); /* ?? */
emu10k_write_reg(devc, SCS0, 0, 0x2109204);
emu10k_write_reg(devc, SCS1, 0, 0x2109204);
emu10k_write_reg(devc, SCS2, 0, 0x2109204);
emu10k_write_reg(devc, PTBA, 0, devc->pt_paddr);
emu10k_write_reg(devc, TCBA, 0, 0x0);
emu10k_write_reg(devc, TCBS, 0, 0x4);
emu10k_write_reg(devc, AC97SLOT, 0, reg);
emu10k_write_reg(devc, EHC, 0, tmp);
emu10k_write_reg(devc, EHC, 0, tmp);
emu10k_write_reg(devc, SOLL, 0, 0xffffffff);
emu10k_write_reg(devc, SOLH, 0, 0xffffffff);
emu10k_write_reg(devc, gpr + GPR0, 0, value);
emu10k_write_reg(devc, init[i] + GPR0, 0, init[i + 1]);
emu10k_write_reg(devc, AUDIGY_DBG, 0, 0);
emu10k_write_reg(devc, DBG, 0, 0);
emu10k_write_reg(devc, VEDS, i, 0);
emu10k_write_reg(devc, VTFT, i, 0);
emu10k_write_reg(devc, CVCF, i, 0);
emu10k_write_reg(devc, PTAB, i, 0);
emu10k_write_reg(devc, CPF, i, 0);
emu10k_write_reg(devc, ADCSR, 0, 0x0);
emu10k_write_reg(devc, ADCBA, 0, 0x0);
emu10k_write_reg(devc, ADCBA, 0, 0x0);
emu10k_write_reg(devc, PTBA, 0, 0);
emu10k_write_reg(devc, SRDA, voice, srda);
emu10k_write_reg(devc, FXRT, voice, fxrt);
emu10k_write_reg(devc, reg, 0, value);
emu10k_write_reg(devc, PTAB, voice, tmp | (send[0] << 8) | send[1]);
emu10k_write_reg(devc, VEDS, voice, 0x0); /* OFF */
emu10k_write_reg(devc, VTFT, voice, 0xffff);
emu10k_write_reg(devc, CVCF, voice, 0xffff);
emu10k_write_reg(devc, CPF, voice, 0x8000);
emu10k_write_reg(devc, SDL, voice, loop_end);
emu10k_write_reg(devc, SCSA, voice, loop_start);
emu10k_write_reg(devc, PTAB, voice, 0);
emu10k_write_reg(devc, QKBCA, voice, start_pos);
emu10k_write_reg(devc, Z1, voice, 0);
emu10k_write_reg(devc, Z2, voice, 0);
emu10k_write_reg(devc, MAPA, voice,
emu10k_write_reg(devc, MAPB, voice,
emu10k_write_reg(devc, VTFT, voice, 0x0000ffff);
emu10k_write_reg(devc, CVCF, voice, 0x0000ffff);
emu10k_write_reg(devc, MEHA, voice, 0);
emu10k_write_reg(devc, MEDS, voice, 0x7f);
emu10k_write_reg(devc, MLV, voice, 0x8000);
emu10k_write_reg(devc, VLV, voice, 0x8000);
emu10k_write_reg(devc, VFM, voice, 0);
emu10k_write_reg(devc, TMFQ, voice, 0);
emu10k_write_reg(devc, VVFQ, voice, 0);
emu10k_write_reg(devc, MEV, voice, 0x8000);
emu10k_write_reg(devc, VEHA, voice, 0x7f7f); /* OK */
emu10k_write_reg(devc, VEV, voice, 0x8000);
emu10k_write_reg(devc, PEFE_FILTERAMOUNT, voice, 0x7f);
emu10k_write_reg(devc, PEFE_PITCHAMOUNT, voice, 0x00);
emu10k_write_reg(devc, SOLL + offs, 0, tmp);
emu10k_write_reg(devc, CD0 + i, voice, sample);
emu10k_write_reg(devc, CCR_CACHEINVALIDSIZE, voice, 0);
emu10k_write_reg(devc, CCR_READADDRESS, voice, cra);
emu10k_write_reg(devc, CCR_CACHEINVALIDSIZE, voice, ccis);
emu10k_write_reg(devc, IFA, voice, 0xff00);
emu10k_write_reg(devc, VTFT, voice, 0xffffffff);
emu10k_write_reg(devc, CVCF, voice, 0xffffffff);
emu10k_write_reg(devc, PTRX_PITCHTARGET, voice, pitch_target);
emu10k_write_reg(devc, CPF_CURRENTPITCH, voice, pitch_target);
emu10k_write_reg(devc, IP, voice, initial_pitch);
emu10k_write_reg(devc, IFA, voice, 0xffff);
emu10k_write_reg(devc, VTFT, voice, 0xffff);
emu10k_write_reg(devc, PTRX_PITCHTARGET, voice, 0);
emu10k_write_reg(devc, CPF_CURRENTPITCH, voice, 0);
emu10k_write_reg(devc, IP, voice, 0);
emu10k_write_reg(devc, IFA, voice, 0xffff);
emu10k_write_reg(devc, VEDS, voice, 0x0);
emu10k_write_reg(devc, VTFT, voice, 0xffff);
emu10k_write_reg(devc, PTAB, voice, 0x0);
emu10k_write_reg(devc, IFA, voice + 1, 0xffff);
emu10k_write_reg(devc, VEDS, voice + 1, 0x0);
emu10k_write_reg(devc, VTFT, voice + 1, 0xffff);
emu10k_write_reg(devc, PTAB, voice + 1, 0x0);
emu10k_write_reg(devc, VEDS, 0, 0x7f7f);
emu10k_write_reg(devc, VEDS, 1, 0x7f7f);
emu10k_write_reg(devc, VEDS, 2, 0x7f7f);
emu10k_write_reg(devc, VEDS, 3, 0x7f7f);
emu10k_write_reg(devc, VEDS, 4, 0x7f7f);
emu10k_write_reg(devc, VEDS, 5, 0x7f7f);
emu10k_write_reg(devc, VEDS, 6, 0x7f7f);
emu10k_write_reg(devc, VEDS, 7, 0x7f7f);
emu10k_write_reg(devc, ADCSR, 0, tmp); /* GO */
emu10k_write_reg(devc, ADCSR, 0, 0);
emu10k_write_reg(devc, ADCBA, 0, portc->buf_paddr);
emu10k_write_reg(devc, ADCBS, 0, sz);
emu10k_write_reg(devc, ADCSR, 0, 0); /* reset for phase */