ecore_rd
u32 ecore_rd(struct ecore_hwfn *p_hwfn,
if (ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED) & 0x20000000) {
dest[i] = ecore_rd(p_hwfn, p_ptt, addr);
dest[i] = ecore_rd(p_hwfn, p_ptt, addr);
public_data_addr = ecore_rd(p_hwfn, p_ptt, MISC_REG_SHARED_MEM_ADDR) | MCP_REG_SCRATCH;
global_section_offsize = ecore_rd(p_hwfn, p_ptt, global_section_offsize_addr);
mfw_ver = ecore_rd(p_hwfn, p_ptt, global_section_addr + offsetof(struct public_global, mfw_ver));
reg_val[i] = ecore_rd(p_hwfn, p_ptt, s_reset_regs_defs[i].addr);
old_reset_reg_val = ecore_rd(p_hwfn, p_ptt, dbg_reset_reg_addr);
if (dev_data->block_in_reset[storm->block_id] || ecore_rd(p_hwfn, p_ptt, storm->sem_sync_dbg_empty_addr)) {
dump_buf[offset + INT_BUF_LINE_SIZE_IN_DWORDS - 1 - i] = ecore_rd(p_hwfn, p_ptt, reg_addr);
last_written_line = ecore_rd(p_hwfn, p_ptt, DBG_REG_INTR_BUFFER_WR_PTR);
if (ecore_rd(p_hwfn, p_ptt, DBG_REG_WRAP_ON_INT_BUFFER)) {
if (!ecore_rd(p_hwfn, p_ptt, DBG_REG_INTR_BUFFER_RD_PTR))
next_wr_phys_addr.lo = ecore_rd(p_hwfn, p_ptt, DBG_REG_EXT_BUFFER_WR_PTR);
next_wr_phys_addr.hi = ecore_rd(p_hwfn, p_ptt, DBG_REG_EXT_BUFFER_WR_PTR + BYTES_IN_DWORD);
if (ecore_rd(p_hwfn, p_ptt, DBG_REG_WRAP_ON_EXT_BUFFER))
ecore_rd(p_hwfn, p_ptt, DWORDS_TO_BYTES(reg_data->sts_clr_address));
*(dump_buf + offset) = ecore_rd(p_hwfn, p_ptt, byte_addr);
*(dump_buf + offset) = ecore_rd(p_hwfn, p_ptt, rd_reg_addr);
#define ARR_REG_RD(dev, ptt, addr, arr, arr_size) for (i = 0; i < (arr_size); i++) (arr)[i] = ecore_rd(dev, ptt, addr)
*(bytes_buf++) = (u8)ecore_rd(p_hwfn, p_ptt, data_lo_addr);
*(bytes_buf++) = (u8)ecore_rd(p_hwfn, p_ptt, data_hi_addr);
if (ecore_rd(p_hwfn, p_ptt, DBG_REG_DBG_BLOCK_ON))
switch (ecore_rd(p_hwfn, p_ptt, MISC_REG_PORT_MODE)) {
spad_trace_offsize = ecore_rd(p_hwfn, p_ptt, MCP_SPAD_TRACE_OFFSIZE_ADDR);
signature = ecore_rd(p_hwfn, p_ptt, *trace_data_grc_addr + offsetof(struct mcp_trace, signature));
*trace_data_size = ecore_rd(p_hwfn, p_ptt, *trace_data_grc_addr + offsetof(struct mcp_trace, size));
spad_trace_offsize = ecore_rd(p_hwfn, p_ptt, MCP_SPAD_TRACE_OFFSIZE_ADDR);
*running_bundle_id = ecore_rd(p_hwfn, p_ptt, running_mfw_addr);
fifo_has_data = ecore_rd(p_hwfn, p_ptt, GRC_REG_TRACE_FIFO_VALID_DATA) > 0;
fifo_has_data = ecore_rd(p_hwfn, p_ptt, GRC_REG_TRACE_FIFO_VALID_DATA) > 0;
fifo_has_data = ecore_rd(p_hwfn, p_ptt, IGU_REG_ERROR_HANDLING_DATA_VALID) > 0;
fifo_has_data = ecore_rd(p_hwfn, p_ptt, IGU_REG_ERROR_HANDLING_DATA_VALID) > 0;
override_window_dwords = ecore_rd(p_hwfn, p_ptt, GRC_REG_NUMBER_VALID_OVERRIDE_WINDOW) * PROTECTION_OVERRIDE_ELEMENT_DWORDS;
next_list_idx = ecore_rd(p_hwfn, p_ptt, next_list_idx_addr);
if (ecore_rd(p_hwfn, p_ptt, DBG_REG_DBG_BLOCK_ON))
if (storm_bus->enabled && !ecore_rd(p_hwfn, p_ptt, storm->sem_sync_dbg_empty_addr))
u32 trigger_state = ecore_rd(p_hwfn, p_ptt, DBG_REG_TRIGGER_STATUS_CUR_STATE);
sts_val = ecore_rd(p_hwfn, p_ptt, sts_addr);
reg_result->mask_val = ecore_rd(p_hwfn, p_ptt, DWORDS_TO_BYTES(reg_data->mask_address));
!(ecore_rd(p_hwfn, p_ptt, s_reset_regs_defs[reset_reg].addr) & (1 << block->reset_bit_offset)) : true;
val = ecore_rd(p_hwfn, p_hwfn->p_main_ptt, bar_reg);
if (ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_CFG_DONE) == 1)
val = ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0);
ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) |
(ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) &
xmac_rxctrl = ecore_rd(p_hwfn, p_ptt,
val = ecore_rd(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV);
prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP);
prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP);
prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE);
prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE);
prs_reg = ecore_rd(p_hwfn, p_ptt,
prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
val = ecore_rd(p_hwfn, p_ptt,
if ((!ecore_rd(p_hwfn, p_ptt,
(!ecore_rd(p_hwfn, p_ptt,
(u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
(u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
u32 val = ecore_rd(p_hwfn, p_ptt, addr);
wake_info->wk_info = ecore_rd(hwfn, hwfn->p_main_ptt,
wake_info->wk_details = ecore_rd(hwfn, hwfn->p_main_ptt,
wake_info->wk_pkt_len = ecore_rd(hwfn, hwfn->p_main_ptt,
buf[i] = ecore_rd(hwfn, hwfn->p_main_ptt,
nvm_cfg_addr = ecore_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
nvm_cfg1_offset = ecore_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
core_cfg = ecore_rd(p_hwfn, p_ptt, addr);
dcbx_mode = ecore_rd(p_hwfn, p_ptt,
link_temp = ecore_rd(p_hwfn, p_ptt,
link_temp = ecore_rd(p_hwfn, p_ptt,
link_temp = ecore_rd(p_hwfn, p_ptt, port_cfg_addr +
generic_cont0 = ecore_rd(p_hwfn, p_ptt, addr);
device_capabilities = ecore_rd(p_hwfn, p_ptt, addr);
reg_function_hide = ecore_rd(p_hwfn, p_ptt,
port_mode = ecore_rd(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB);
port = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
port = ecore_rd(p_hwfn, p_ptt,
p_dev->chip_num = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
p_dev->chip_rev = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
tmp = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
p_dev->chip_bond_id = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
p_dev->chip_metal = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
tmp = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
en = ecore_rd(p_hwfn, p_ptt,
if (ecore_rd(p_hwfn, p_ptt,
if (ecore_rd(p_hwfn, p_ptt,
en = ecore_rd(p_hwfn, p_ptt,
if (!ecore_rd(p_hwfn, p_ptt,
if (!ecore_rd(p_hwfn, p_ptt,
if (!(ecore_rd(p_hwfn, p_ptt,
if (ecore_rd(p_hwfn, p_ptt,
if (ecore_rd(p_hwfn, p_ptt,
lock_status = ecore_rd(p_hwfn, p_ptt, hw_lock_cntr_reg);
lock_status = ecore_rd(p_hwfn, p_ptt, hw_lock_cntr_reg);
lock_status = ecore_rd(p_hwfn, p_ptt, hw_lock_cntr_reg);
u32 ecore_rd(struct ecore_hwfn *p_hwfn,
reg_val = ecore_rd(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN);
reg_val = ecore_rd(p_hwfn, p_ptt, NIG_REG_ENC_TYPE_ENABLE);
reg_val = ecore_rd(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN);
reg_val = ecore_rd(p_hwfn, p_ptt, NIG_REG_ENC_TYPE_ENABLE);
reg_val = ecore_rd(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN);
rfs_cm_hdr_event_id = ecore_rd(p_hwfn, p_ptt, PRS_REG_CM_HDR_GFT);
rfs_cm_hdr_event_id = ecore_rd(p_hwfn, p_ptt, PRS_REG_CM_HDR_GFT);
cam_line.cam_line_mapped.camline = ecore_rd(p_hwfn, p_ptt, PRS_REG_GFT_CAM + CAM_LINE_SIZE*pf_id);
reg_val = ecore_rd(p_hwfn, p_ptt, QM_REG_SDMCMDREADY);
val = ecore_rd(p_hwfn, p_ptt, addr);
val = ecore_rd(p_hwfn, p_ptt, addr);
val = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
aeu_mask = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
u32 tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_STATE);
u32 tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, PSWHST_REG_VF_DISABLED_ERROR_VALID);
addr = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
data = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
tmp = ecore_rd(p_hwfn, p_ptt, MISC_REG_AEU_ENABLE4_IGU_OUT_0);
val = ecore_rd(p_hwfn, p_ptt, sb_bit_addr);
val = ecore_rd(p_hwfn, p_ptt,
val = ecore_rd(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION);
tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
addr = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
data = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
length = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
rval = ecore_rd(p_hwfn, p_ptt,
u32 val = ecore_rd(p_hwfn, p_ptt,
p_info->igu_prod = ecore_rd(p_hwfn, p_ptt,
p_info->igu_cons = ecore_rd(p_hwfn, p_ptt,
p_info->pi[i] = (u16)ecore_rd(p_hwfn, p_ptt,
tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
tmp2 = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
addr_lo = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
addr_hi = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
details = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
addr_lo = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
addr_hi = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
details = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
addr_lo = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
addr_hi = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
addr_lo = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
addr_hi = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
details = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
reason = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, DORQ_REG_DB_DROP_REASON) &
u32 details = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
u32 val = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
val = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, TM_REG_INT_MASK_1);
igu_mask = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
val = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg);
val = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg);
aeu_inv_arr[i] = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
en = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en);
en = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en);
u32 mfw_mb_offsize = ecore_rd(p_hwfn, p_ptt, addr);
u32 mfw_path_offsize = ecore_rd(p_hwfn, p_ptt, addr);
disabled_vfs[i] = ecore_rd(p_hwfn, p_ptt,
u32 mfw_func_offsize = ecore_rd(p_hwfn, p_ptt, addr);
transceiver_state = ecore_rd(p_hwfn, p_ptt,
eee_status = ecore_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
status = ecore_rd(p_hwfn, p_ptt,
tmp = ecore_rd(p_hwfn, p_ptt,
path_offsize = ecore_rd(p_hwfn, p_ptt, path_offsize_addr);
proc_kill_cnt = ecore_rd(p_hwfn, p_ptt,
u32 mfw_path_offsize = ecore_rd(p_hwfn, p_ptt, addr);
((u32 *)p_data)[i] = ecore_rd(p_hwfn, p_ptt,
p_info->public_base = ecore_rd(p_hwfn, p_ptt, MISC_REG_SHARED_MEM_ADDR);
drv_mb_offsize = ecore_rd(p_hwfn, p_ptt,
global_offsize = ecore_rd(p_hwfn, p_ptt, addr);
p_mdump_info->reason = ecore_rd(p_hwfn, p_ptt,
mfw_mb_offsize = ecore_rd(p_hwfn, p_ptt,
p_info->mfw_mb_length = (u16)ecore_rd(p_hwfn, p_ptt,
p_info->mcp_hist = (u16)ecore_rd(p_hwfn, p_ptt,
global_offsize = ecore_rd(p_hwfn, p_ptt,
*p_mfw_ver = ecore_rd(p_hwfn, p_ptt,
*p_running_bundle_id = ecore_rd(p_hwfn, p_ptt,
nvm_cfg_addr = ecore_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
nvm_cfg1_offset = ecore_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
*p_mbi_ver = ecore_rd(p_hwfn, p_ptt, mbi_ver_addr) &
*p_media_type = ecore_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
flash_size = ecore_rd(p_hwfn, p_ptt, MCP_REG_NVM_CFG4);
cpu_state = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_STATE);
ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE), cpu_state);
cpu_mode = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE);
cpu_state = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_STATE);
addr = ecore_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
size = ecore_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
org_mcp_reset_seq = ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
} while ((org_mcp_reset_seq == ecore_rd(p_hwfn, p_ptt,
ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) {
cpu_mode = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE);
cpu_state = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_STATE);
cpu_pc_0 = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_PROGRAM_COUNTER);
cpu_pc_1 = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_PROGRAM_COUNTER);
cpu_pc_2 = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_PROGRAM_COUNTER);
ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) {
ecore_rd(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset))
u32 mfw_mb_offsize = ecore_rd(p_hwfn, p_ptt, addr);
transceiver_state = ecore_rd(p_hwfn, p_ptt,
nvm_cfg_addr = ecore_rd(p_hwfn, p_ptt,
nvm_cfg1_offset = ecore_rd(p_hwfn, p_ptt,
gpio = (u16)ecore_rd(p_hwfn, p_ptt,
nvm_cfg_addr = ecore_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
nvm_cfg1_offset = ecore_rd(p_hwfn, p_ptt, nvm_cfg_addr +
u8 is_bb = ((ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_NUM) & 0x8070)
core_cfg = ecore_rd(p_hwfn, p_ptt, nvm_cfg1_addr +
data_lo = ecore_rd(p_hwfn, p_ptt,
data_hi = ecore_rd(p_hwfn, p_ptt,
ret = ecore_rd(p_hwfn, p_hwfn->p_main_ptt, addr);
transceiver_state = ecore_rd(hwfn, ptt, hwfn->mcp_info->port_addr +
link->media = ecore_rd(hwfn, ptt, hwfn->mcp_info->port_addr +
link->txr_data = ecore_rd(hwfn, ptt, hwfn->mcp_info->port_addr +