usr/src/uts/common/io/avintr.c

676

xc_call(0, 0, 0, CPUSET2BV(poke), (xc_func_t)siron_poke_intr);

usr/src/uts/i86pc/io/pcplusmp/apic_common.c

408

xc_call(0, 0, 0, CPUSET2BV(cpu_set),

usr/src/uts/i86pc/io/pcplusmp/apic_common.c

411

xc_call(0, 0, 0, CPUSET2BV(cpu_set),

usr/src/uts/i86pc/os/cmi_hw.c

1776

xc_call(0, 0, 0, CPUSET2BV(set),

usr/src/uts/i86pc/os/cmi_hw.c

254

CPUSET2BV(cpus), func);

usr/src/uts/i86pc/os/cpupm/cpupm_throttle.c

222

CPUSET2BV(set), cpupm_tstate_transition);

usr/src/uts/i86pc/os/cpupm/pwrnow.c

161

CPUSET2BV(set), pwrnow_pstate_transition);

usr/src/uts/i86pc/os/cpupm/speedstep.c

175

xc_call((xc_arg_t)req_state, 0, 0, CPUSET2BV(set),

usr/src/uts/i86pc/os/dtrace_subr.c

145

xc_sync((xc_arg_t)func, (xc_arg_t)arg, 0, CPUSET2BV(set),

usr/src/uts/i86pc/os/fastboot.c

1359

xc_priority((xc_arg_t)&newkernel, 0, 0, CPUSET2BV(cpuset),

usr/src/uts/i86pc/os/machdep.c

413

xc_priority(0, 0, 0, CPUSET2BV(xcset), mach_cpu_halt);

usr/src/uts/i86pc/os/machdep.c

950

xc_priority(0, 0, 0, CPUSET2BV(xcset), (xc_func_t)panic_idle);

usr/src/uts/i86pc/os/mp_call.c

89

xc_call((xc_arg_t)arg1, (xc_arg_t)arg2, 0, CPUSET2BV(set),

usr/src/uts/i86pc/os/x_call.c

112

static volatile ulong_t *xc_priority_set = CPUSET2BV(xc_priority_set_store);

usr/src/uts/i86pc/os/x_call.c

659

xc_priority_common((xc_func_t)func, 0, 0, 0, CPUSET2BV(set));

usr/src/uts/i86pc/vm/hat_i86.c

2642

CPUSET2BV(cpus_to_shootdown), hati_demap_func);

usr/src/uts/intel/io/vmm/vmm_sol_glue.c

96

CPUSET2BV(cpuset), (xc_func_t)invalidate_cache);

usr/src/uts/intel/kdi/kdi_idt.c

337

xc_call(0, 0, 0, CPUSET2BV(cpuset), kdi_cpu_activate);

usr/src/uts/intel/kdi/kdi_idt.c

355

xc_call(0, 0, 0, CPUSET2BV(cpuset), kdi_cpu_deactivate);

usr/src/uts/intel/os/cpuid.c

8347

xc_sync((xc_arg_t)argdata, B_TRUE, 0, CPUSET2BV(cpuset),

usr/src/uts/intel/os/cpuid.c

8349

xc_sync((xc_arg_t)argdata, B_FALSE, 0, CPUSET2BV(cpuset),

usr/src/uts/intel/os/hma.c

332

xc_call((xc_arg_t)flag, (xc_arg_t)eptp, 0, CPUSET2BV(set),

usr/src/uts/intel/os/hma.c

435

xc_call(0, 0, 0, CPUSET2BV(set), hma_vmx_cpu_vmxon);

usr/src/uts/intel/os/hma.c

450

CPUSET2BV(set), hma_vmx_invept_xcall);

usr/src/uts/intel/os/hma.c

955

xc_call(0, 0, 0, CPUSET2BV(set), hma_svm_cpu_activate);

usr/src/uts/intel/os/microcode.c

302

xc_sync((xc_arg_t)uusp, 0, 0, CPUSET2BV(cpuset), ucode_write);

usr/src/uts/intel/sys/mutex_impl.h

116

xc_call(0, 0, 0, CPUSET2BV(set), \