doorbell
#define NVME_DOORBELL_OFFSET offsetof(struct nvme_registers, doorbell)
uint64_t doorbell;
doorbell = (cmd_sn << 4) | cq_cmd;
doorbell = (doorbell << 24) | cqn;
doorbell = (doorbell << 32) | cq_param;
((tavor_hw_uar_t *)ia_uar)->cq = HTOBE_64(doorbell);
(uint32_t)HTOBE_32(doorbell >> 32);
(uint32_t)HTOBE_32(doorbell & 0x00000000ffffffff);
dapls_atomic_assign_64(HTOBE_64(doorbell),
uint64_t doorbell;
doorbell = ((uint64_t)1 << ARBEL_QPSNDDB_WQE_CNT_SHIFT) |
((tavor_hw_uar_t *)ia_uar)->send = HTOBE_64(doorbell);
(uint32_t)HTOBE_32(doorbell >> 32);
(uint32_t)HTOBE_32(doorbell & 0x00000000ffffffff);
dapls_atomic_assign_64(HTOBE_64(doorbell),
uint64_t doorbell;
doorbell = (cmd_sn | cq_cmd | cqn);
doorbell = (doorbell << 32) | cq_param;
((tavor_hw_uar_t *)ia_uar)->cq = HTOBE_64(doorbell);
(uint32_t)HTOBE_32(doorbell >> 32);
(uint32_t)HTOBE_32(doorbell & 0x00000000ffffffff);
dapls_atomic_assign_64(HTOBE_64(doorbell),
uint64_t doorbell;
doorbell = qpn << 8;
((tavor_hw_uar_t *)ia_uar)->send = HTOBE_64(doorbell);
(uint32_t)HTOBE_32(doorbell >> 32);
(uint32_t)HTOBE_32(doorbell & 0x00000000ffffffff);
dapls_atomic_assign_64(HTOBE_64(doorbell),
(uint32_t)HTOBE_32(doorbell >> 32);
(uint32_t)HTOBE_32(doorbell & 0x00000000ffffffff);
dapls_atomic_assign_64(HTOBE_64(doorbell),
uint64_t doorbell;
doorbell = (((uint64_t)nda & TAVOR_QPSNDDB_NDA_MASK) <<
((tavor_hw_uar_t *)ia_uar)->send = HTOBE_64(doorbell);
(uint32_t)HTOBE_32(doorbell >> 32);
(uint32_t)HTOBE_32(doorbell & 0x00000000ffffffff);
dapls_atomic_assign_64(HTOBE_64(doorbell),
uint64_t doorbell;
doorbell = (((uint64_t)nda & TAVOR_QPRCVDB_NDA_MASK) <<
((tavor_hw_uar_t *)ia_uar)->recv = HTOBE_64(doorbell);
(uint32_t)HTOBE_32(doorbell >> 32);
(uint32_t)HTOBE_32(doorbell & 0x00000000ffffffff);
dapls_atomic_assign_64(HTOBE_64(doorbell),
uint64_t doorbell;
doorbell = ((uint64_t)cq_cmd << TAVOR_CQDB_CMD_SHIFT) |
((tavor_hw_uar_t *)ia_uar)->cq = HTOBE_64(doorbell);
struct doorbell db = TOE_RX_INIT_ZERO;\
struct doorbell db = TOE_TX_INIT_ZERO;\
goto doorbell;
doorbell:
uint64_t doorbell = 0;
doorbell = ((uint64_t)cq_cmd << TAVOR_CQDB_CMD_SHIFT) |
doorbell);
uint64_t doorbell = 0;
doorbell = ((uint64_t)eq_cmd << TAVOR_EQDB_CMD_SHIFT) |
doorbell);
uint64_t doorbell = 0;
doorbell = (((uint64_t)nda & TAVOR_QPSNDDB_NDA_MASK) <<
doorbell);
uint64_t doorbell = 0;
doorbell = (((uint64_t)nda & TAVOR_QPRCVDB_NDA_MASK) <<
doorbell);
caddr_t doorbell;
qede->doorbell;
&qede->doorbell,
qede->pci_bar2_base = (unsigned long)qede->doorbell;
edev->doorbells = (void *)qede->doorbell;
uint32_t doorbell;
doorbell = mptsas_hirrd(mpt, &mpt->m_reg->Doorbell);
if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
doorbell &= MPI2_DOORBELL_DATA_MASK;
"code: %04x", doorbell);
uint32_t doorbell;
doorbell = G32(s, sis_ctrl_to_host_doorbell);
if (doorbell & SIS_CMD_COMPLETE)
uint32_t doorbell;
doorbell = G32(s, sis_ctrl_to_host_doorbell);
if ((doorbell & SIS_REENABLE_SIS_MODE) == 0) {
#define HERMON_UAR_DOORBELL(state, uarhdl, hs_uar, doorbell) { \
ddi_put64(uarhdl, hs_uar, doorbell); \
#define HERMON_UAR_DOORBELL(state, uarhdl, hs_uar, doorbell) { \
ddi_put64(uarhdl, hs_uar, doorbell); \
#define TAVOR_UAR_DOORBELL(state, ts_uar, doorbell) { \
ddi_put64(state->ts_reg_uarhdl, ts_uar, doorbell); \
#define TAVOR_UAR_DOORBELL(state, ts_uar, doorbell) { \
ddi_put64(state->ts_reg_uarhdl, ts_uar, doorbell); \