usr/src/cmd/mdb/common/modules/qlc/qlc.c

2483

for (cnt = 0; cnt < sizeof (fw->dma_reg) / 2; cnt++) {

usr/src/cmd/mdb/common/modules/qlc/qlc.c

2487

mdb_printf("%04x ", fw->dma_reg[cnt]);

usr/src/uts/common/io/fibre-channel/fca/qlc/ql_api.c

12536

for (cnt = 0; cnt < sizeof (fw->dma_reg) / 2; cnt++) {

usr/src/uts/common/io/fibre-channel/fca/qlc/ql_api.c

12540

(void) sprintf(bp, "%04x ", fw->dma_reg[cnt]);

usr/src/uts/common/io/fibre-channel/fca/qlc/ql_api.c

14233

(void) ql_read_regs(ha, fw->dma_reg, ha->iobase + 0x20,

usr/src/uts/common/io/fibre-channel/fca/qlc/ql_api.c

14234

sizeof (fw->dma_reg) / 2, 16);

usr/src/uts/common/io/fibre-channel/fca/qlc/ql_api.c

14444

(void) ql_read_regs(ha, fw->dma_reg, ha->iobase + 0x80,

usr/src/uts/common/io/fibre-channel/fca/qlc/ql_api.c

14445

sizeof (fw->dma_reg) / 2, 16);

usr/src/uts/common/sys/fibre-channel/fca/qlc/ql_init.h

741

uint16_t dma_reg[48];

usr/src/uts/sun/io/fd.c

6299

struct cheerio_dma_reg *dma_reg;

usr/src/uts/sun/io/fd.c

6300

dma_reg = (struct cheerio_dma_reg *)fdc->c_dma_regs;

usr/src/uts/sun/io/fd.c

6301

ddi_put32(fdc->c_handlep_dma, &dma_reg->fdc_dbcr, count);

usr/src/uts/sun/io/fd.c

6303

struct sb_dma_reg *dma_reg;

usr/src/uts/sun/io/fd.c

6305

dma_reg = (struct sb_dma_reg *)fdc->c_dma_regs;

usr/src/uts/sun/io/fd.c

6309

(ushort_t *)&dma_reg->sb_dma_regs[DMA_0WCNT],

usr/src/uts/sun/io/fd.c

6314

(ushort_t *)&dma_reg->sb_dma_regs[DMA_1WCNT],

usr/src/uts/sun/io/fd.c

6319

(ushort_t *)&dma_reg->sb_dma_regs[DMA_2WCNT],

usr/src/uts/sun/io/fd.c

6324

(ushort_t *)&dma_reg->sb_dma_regs[DMA_3WCNT],

usr/src/uts/sun/io/fd.c

6346

struct cheerio_dma_reg *dma_reg;

usr/src/uts/sun/io/fd.c

6347

dma_reg = (struct cheerio_dma_reg *)fdc->c_dma_regs;

usr/src/uts/sun/io/fd.c

6348

retval = ddi_get32(fdc->c_handlep_dma, &dma_reg->fdc_dbcr);

usr/src/uts/sun/io/fd.c

6350

struct sb_dma_reg *dma_reg;

usr/src/uts/sun/io/fd.c

6351

dma_reg = (struct sb_dma_reg *)fdc->c_dma_regs;

usr/src/uts/sun/io/fd.c

6355

(ushort_t *)&dma_reg->sb_dma_regs[DMA_0WCNT]);

usr/src/uts/sun/io/fd.c

6359

(ushort_t *)&dma_reg->sb_dma_regs[DMA_1WCNT]);

usr/src/uts/sun/io/fd.c

6363

(ushort_t *)&dma_reg->sb_dma_regs[DMA_2WCNT]);

usr/src/uts/sun/io/fd.c

6367

(ushort_t *)&dma_reg->sb_dma_regs[DMA_3WCNT]);

usr/src/uts/sun/io/fd.c

6391

struct cheerio_dma_reg *dma_reg;

usr/src/uts/sun/io/fd.c

6392

dma_reg = (struct cheerio_dma_reg *)fdc->c_dma_regs;

usr/src/uts/sun/io/fd.c

6393

ddi_put32(fdc->c_handlep_dma, &dma_reg->fdc_dcsr, DCSR_RESET);

usr/src/uts/sun/io/fd.c

6396

ddi_put32(fdc->c_handlep_dma, &dma_reg->fdc_dcsr, 0);

usr/src/uts/sun/io/fd.c

6398

struct sb_dma_reg *dma_reg;

usr/src/uts/sun/io/fd.c

6399

dma_reg = (struct sb_dma_reg *)fdc->c_dma_regs;

usr/src/uts/sun/io/fd.c

6400

ddi_put8(fdc->c_handlep_dma, &dma_reg->sb_dma_regs[DMAC1_MASK],

usr/src/uts/sun/io/fd.c

6416

struct cheerio_dma_reg *dma_reg;

usr/src/uts/sun/io/fd.c

6417

dma_reg = (struct cheerio_dma_reg *)fdc->c_dma_regs;

usr/src/uts/sun/io/fd.c

6418

retval = ddi_get32(fdc->c_handlep_dma, &dma_reg->fdc_dcsr);

usr/src/uts/sun/io/fd.c

6433

struct cheerio_dma_reg *dma_reg;

usr/src/uts/sun/io/fd.c

6434

dma_reg = (struct cheerio_dma_reg *)fdc->c_dma_regs;

usr/src/uts/sun/io/fd.c

6435

ddi_put32(fdc->c_handlep_dma, &dma_reg->fdc_dacr, address);

usr/src/uts/sun/io/fd.c

6437

struct sb_dma_reg *dma_reg;

usr/src/uts/sun/io/fd.c

6438

dma_reg = (struct sb_dma_reg *)fdc->c_dma_regs;

usr/src/uts/sun/io/fd.c

6442

&dma_reg->sb_dma_regs[DMA_0PAGE],

usr/src/uts/sun/io/fd.c

6445

&dma_reg->sb_dma_regs[DMA_0HPG],

usr/src/uts/sun/io/fd.c

6448

(ushort_t *)&dma_reg->sb_dma_regs[DMA_0ADR],

usr/src/uts/sun/io/fd.c

6453

&dma_reg->sb_dma_regs[DMA_1PAGE],

usr/src/uts/sun/io/fd.c

6456

&dma_reg->sb_dma_regs[DMA_1HPG],

usr/src/uts/sun/io/fd.c

6459

(ushort_t *)&dma_reg->sb_dma_regs[DMA_1ADR],

usr/src/uts/sun/io/fd.c

6464

&dma_reg->sb_dma_regs[DMA_2PAGE],

usr/src/uts/sun/io/fd.c

6467

&dma_reg->sb_dma_regs[DMA_2HPG],

usr/src/uts/sun/io/fd.c

6470

(ushort_t *)&dma_reg->sb_dma_regs[DMA_2ADR],

usr/src/uts/sun/io/fd.c

6475

&dma_reg->sb_dma_regs[DMA_3PAGE],

usr/src/uts/sun/io/fd.c

6478

&dma_reg->sb_dma_regs[DMA_3HPG],

usr/src/uts/sun/io/fd.c

6481

(ushort_t *)&dma_reg->sb_dma_regs[DMA_3ADR],

usr/src/uts/sun/io/fd.c

6503

struct cheerio_dma_reg *dma_reg;

usr/src/uts/sun/io/fd.c

6504

dma_reg = (struct cheerio_dma_reg *)fdc->c_dma_regs;

usr/src/uts/sun/io/fd.c

6506

ddi_put32(fdc->c_handlep_dma, &dma_reg->fdc_dcsr,

usr/src/uts/sun/io/fd.c

6509

ddi_put32(fdc->c_handlep_dma, &dma_reg->fdc_dcsr,

usr/src/uts/sun/io/fd.c

6514

struct sb_dma_reg *dma_reg;

usr/src/uts/sun/io/fd.c

6515

dma_reg = (struct sb_dma_reg *)fdc->c_dma_regs;

usr/src/uts/sun/io/fd.c

6524

ddi_put8(fdc->c_handlep_dma, &dma_reg->sb_dma_regs[DMAC1_MODE],

usr/src/uts/sun/io/fd.c

6528

&dma_reg->sb_dma_regs[DMAC1_ALLMASK], ~chn_mask);

usr/src/uts/sun/io/fd.c

6543

struct cheerio_dma_reg *dma_reg;

usr/src/uts/sun/io/fd.c

6544

dma_reg = (struct cheerio_dma_reg *)fdc->c_dma_regs;

usr/src/uts/sun/io/fd.c

6545

ddi_put32(fdc->c_handlep_dma, &dma_reg->fdc_dcsr, val);

usr/src/uts/sun/io/fd.c

6552

struct sb_dma_reg *dma_reg;

usr/src/uts/sun/io/fd.c

6553

dma_reg = (struct sb_dma_reg *)fdc->c_dma_regs;

usr/src/uts/sun/io/fd.c

6556

&dma_reg->sb_dma_regs[DMAC1_ALLMASK], 0);