Symbol: df_reg_def_t
usr/src/uts/intel/io/amdzen/amdzen.c
283
amdzen_df_read_regdef(amdzen_t *azn, amdzen_df_t *df, const df_reg_def_t def,
usr/src/uts/intel/io/amdzen/amdzen.c
286
df_reg_def_t ficaa;
usr/src/uts/intel/io/amdzen/amdzen.c
287
df_reg_def_t ficad;
usr/src/uts/intel/io/amdzen/amdzen.c
333
const df_reg_def_t def)
usr/src/uts/intel/io/amdzen/amdzen.c
344
amdzen_df_read32_bcast(amdzen_t *azn, amdzen_df_t *df, const df_reg_def_t def)
usr/src/uts/intel/io/amdzen/amdzen.c
351
amdzen_df_read64_bcast(amdzen_t *azn, amdzen_df_t *df, const df_reg_def_t def)
usr/src/uts/intel/io/amdzen/amdzen.c
564
amdzen_c_df_read32(uint_t dfno, uint8_t inst, const df_reg_def_t def,
usr/src/uts/intel/io/amdzen/amdzen.c
589
amdzen_c_df_read64(uint_t dfno, uint8_t inst, const df_reg_def_t def,
usr/src/uts/intel/io/amdzen/amdzen.c
614
amdzen_c_df_read32_bcast(uint_t dfno, const df_reg_def_t def, uint32_t *valp)
usr/src/uts/intel/io/amdzen/amdzen.c
638
amdzen_c_df_read64_bcast(uint_t dfno, const df_reg_def_t def, uint64_t *valp)
usr/src/uts/intel/io/amdzen/amdzen.c
929
df_reg_def_t rd = DF_FBICNT;
usr/src/uts/intel/io/amdzen/amdzen_client.h
101
extern int amdzen_c_df_read32_bcast(uint_t, const df_reg_def_t, uint32_t *);
usr/src/uts/intel/io/amdzen/amdzen_client.h
102
extern int amdzen_c_df_read64_bcast(uint_t, const df_reg_def_t, uint64_t *);
usr/src/uts/intel/io/amdzen/amdzen_client.h
98
extern int amdzen_c_df_read32(uint_t, uint8_t, const df_reg_def_t, uint32_t *);
usr/src/uts/intel/io/amdzen/amdzen_client.h
99
extern int amdzen_c_df_read64(uint_t, uint8_t, const df_reg_def_t, uint64_t *);
usr/src/uts/intel/io/amdzen/zen_udf.c
78
df_reg_def_t def;
usr/src/uts/intel/io/amdzen/zen_umc.c
2219
const df_reg_def_t remapA[ZEN_UMC_MAX_CS_REMAPS] = {
usr/src/uts/intel/io/amdzen/zen_umc.c
2222
const df_reg_def_t remapB[ZEN_UMC_MAX_CS_REMAPS] = {
usr/src/uts/intel/io/amdzen/zen_umc.c
2225
const df_reg_def_t remapC[ZEN_UMC_MAX_CS_REMAPS] = {
usr/src/uts/intel/io/amdzen/zen_umc.c
2278
const df_reg_def_t milan_remap0[ZEN_UMC_MILAN_CS_NREMAPS] = {
usr/src/uts/intel/io/amdzen/zen_umc.c
2280
const df_reg_def_t milan_remap1[ZEN_UMC_MILAN_CS_NREMAPS] = {
usr/src/uts/intel/io/amdzen/zen_umc.c
2282
const df_reg_def_t dfv4_remapA[ZEN_UMC_MAX_CS_REMAPS] = {
usr/src/uts/intel/io/amdzen/zen_umc.c
2285
const df_reg_def_t dfv4_remapB[ZEN_UMC_MAX_CS_REMAPS] = {
usr/src/uts/intel/io/amdzen/zen_umc.c
2288
const df_reg_def_t *remapA, *remapB;
usr/src/uts/intel/io/amdzen/zen_umc.c
2365
df_reg_def_t hole;
usr/src/uts/intel/io/amdzen/zen_umc.c
3552
df_reg_def_t off_reg;
usr/src/uts/intel/sys/amdzen/df.h
1000
#define DF_FIDMASK2_V3P5 (df_reg_def_t){ .drd_gens = DF_REV_3P5, \
usr/src/uts/intel/sys/amdzen/df.h
1004
#define DF_FIDMASK2_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \
usr/src/uts/intel/sys/amdzen/df.h
1020
#define DF_DIEMASK_CPU_V2 (df_reg_def_t){ .drd_gens = DF_REV_2, \
usr/src/uts/intel/sys/amdzen/df.h
1024
#define DF_DIEMASK_APU_V2 (df_reg_def_t){ .drd_gens = DF_REV_2, \
usr/src/uts/intel/sys/amdzen/df.h
1050
#define DF_CCD_EN_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \
usr/src/uts/intel/sys/amdzen/df.h
1065
#define DF_PHYS_CORE_EN0_V3 (df_reg_def_t){ .drd_gens = DF_REV_ALL_3, \
usr/src/uts/intel/sys/amdzen/df.h
1069
#define DF_PHYS_CORE_EN1_V3 (df_reg_def_t){ .drd_gens = DF_REV_ALL_3, \
usr/src/uts/intel/sys/amdzen/df.h
1073
#define DF_PHYS_CORE_EN0_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \
usr/src/uts/intel/sys/amdzen/df.h
1077
#define DF_PHYS_CORE_EN1_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \
usr/src/uts/intel/sys/amdzen/df.h
1081
#define DF_PHYS_CORE_EN2_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \
usr/src/uts/intel/sys/amdzen/df.h
1085
#define DF_PHYS_CORE_EN3_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \
usr/src/uts/intel/sys/amdzen/df.h
1089
#define DF_PHYS_CORE_EN4_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \
usr/src/uts/intel/sys/amdzen/df.h
1093
#define DF_PHYS_CORE_EN5_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \
usr/src/uts/intel/sys/amdzen/df.h
1104
#define DF_NP2_CONFIG_V3 (df_reg_def_t){ .drd_gens = DF_REV_3, \
usr/src/uts/intel/sys/amdzen/df.h
1118
#define DF_CCMCFG4_V4 (df_reg_def_t){ .drd_gens = DF_REV_4, \
usr/src/uts/intel/sys/amdzen/df.h
1132
#define DF_FICAA_V2 (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \
usr/src/uts/intel/sys/amdzen/df.h
1137
#define DF_FICAA_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \
usr/src/uts/intel/sys/amdzen/df.h
1156
#define DF_FICAD_LO_V2 (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \
usr/src/uts/intel/sys/amdzen/df.h
1160
#define DF_FICAD_HI_V2 (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \
usr/src/uts/intel/sys/amdzen/df.h
1164
#define DF_FICAD_LO_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \
usr/src/uts/intel/sys/amdzen/df.h
1168
#define DF_FICAD_HI_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \
usr/src/uts/intel/sys/amdzen/df.h
1176
df_reg_valid(const df_rev_t rev, const df_reg_def_t def)
usr/src/uts/intel/sys/amdzen/df.h
1204
#define DF_SYS_FUN_FID1_V3 (df_reg_def_t){ .drd_gens = DF_REV_ALL_3, \
usr/src/uts/intel/sys/amdzen/df.h
1211
#define DF_SYS_FUN_FID1_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \
usr/src/uts/intel/sys/amdzen/df.h
1220
#define DF_SYS_FUN_FID2_V3 (df_reg_def_t){ .drd_gens = DF_REV_ALL_3, \
usr/src/uts/intel/sys/amdzen/df.h
1227
#define DF_SYS_FUN_FID2_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \
usr/src/uts/intel/sys/amdzen/df.h
132
#define DF_FBICNT (df_reg_def_t){ .drd_gens = DF_REV_ALL, \
usr/src/uts/intel/sys/amdzen/df.h
143
#define DF_FBIINFO0 (df_reg_def_t){ .drd_gens = DF_REV_ALL, \
usr/src/uts/intel/sys/amdzen/df.h
230
#define DF_FBIINFO1 (df_reg_def_t){ .drd_gens = DF_REV_ALL_23 | \
usr/src/uts/intel/sys/amdzen/df.h
242
#define DF_FBIINFO2 (df_reg_def_t){ .drd_gens = DF_REV_ALL_23 | \
usr/src/uts/intel/sys/amdzen/df.h
252
#define DF_FBIINFO3 (df_reg_def_t){ .drd_gens = DF_REV_ALL, \
usr/src/uts/intel/sys/amdzen/df.h
267
#define DF_CAPAB (df_reg_def_t){ .drd_gens = DF_REV_ALL, \
usr/src/uts/intel/sys/amdzen/df.h
283
#define DF_SKT0_CS_REMAP0_V3 (df_reg_def_t){ .drd_gens = DF_REV_3, \
usr/src/uts/intel/sys/amdzen/df.h
286
#define DF_SKT1_CS_REMAP0_V3 (df_reg_def_t){ .drd_gens = DF_REV_3, \
usr/src/uts/intel/sys/amdzen/df.h
289
#define DF_SKT0_CS_REMAP1_V3 (df_reg_def_t){ .drd_gens = DF_REV_3, \
usr/src/uts/intel/sys/amdzen/df.h
292
#define DF_SKT1_CS_REMAP1_V3 (df_reg_def_t){ .drd_gens = DF_REV_3, \
usr/src/uts/intel/sys/amdzen/df.h
303
#define DF_CS_REMAP0A_V4 (df_reg_def_t){ .drd_gens = DF_REV_4, \
usr/src/uts/intel/sys/amdzen/df.h
306
#define DF_CS_REMAP0B_V4 (df_reg_def_t){ .drd_gens = DF_REV_4, \
usr/src/uts/intel/sys/amdzen/df.h
309
#define DF_CS_REMAP1A_V4 (df_reg_def_t){ .drd_gens = DF_REV_4, \
usr/src/uts/intel/sys/amdzen/df.h
312
#define DF_CS_REMAP1B_V4 (df_reg_def_t){ .drd_gens = DF_REV_4, \
usr/src/uts/intel/sys/amdzen/df.h
315
#define DF_CS_REMAP2A_V4 (df_reg_def_t){ .drd_gens = DF_REV_4, \
usr/src/uts/intel/sys/amdzen/df.h
318
#define DF_CS_REMAP2B_V4 (df_reg_def_t){ .drd_gens = DF_REV_4, \
usr/src/uts/intel/sys/amdzen/df.h
321
#define DF_CS_REMAP3A_V4 (df_reg_def_t){ .drd_gens = DF_REV_4, \
usr/src/uts/intel/sys/amdzen/df.h
324
#define DF_CS_REMAP3B_V4 (df_reg_def_t){ .drd_gens = DF_REV_4, \
usr/src/uts/intel/sys/amdzen/df.h
337
#define DF_CS_REMAP0A_V4D2 (df_reg_def_t){ .drd_gens = DF_REV_4D2, \
usr/src/uts/intel/sys/amdzen/df.h
340
#define DF_CS_REMAP0B_V4D2 (df_reg_def_t){ .drd_gens = DF_REV_4D2, \
usr/src/uts/intel/sys/amdzen/df.h
343
#define DF_CS_REMAP0C_V4D2 (df_reg_def_t){ .drd_gens = DF_REV_4D2, \
usr/src/uts/intel/sys/amdzen/df.h
346
#define DF_CS_REMAP1A_V4D2 (df_reg_def_t){ .drd_gens = DF_REV_4D2, \
usr/src/uts/intel/sys/amdzen/df.h
349
#define DF_CS_REMAP1B_V4D2 (df_reg_def_t){ .drd_gens = DF_REV_4D2, \
usr/src/uts/intel/sys/amdzen/df.h
352
#define DF_CS_REMAP1C_V4D2 (df_reg_def_t){ .drd_gens = DF_REV_4D2, \
usr/src/uts/intel/sys/amdzen/df.h
355
#define DF_CS_REMAP2A_V4D2 (df_reg_def_t){ .drd_gens = DF_REV_4D2, \
usr/src/uts/intel/sys/amdzen/df.h
358
#define DF_CS_REMAP2B_V4D2 (df_reg_def_t){ .drd_gens = DF_REV_4D2, \
usr/src/uts/intel/sys/amdzen/df.h
361
#define DF_CS_REMAP2C_V4D2 (df_reg_def_t){ .drd_gens = DF_REV_4D2, \
usr/src/uts/intel/sys/amdzen/df.h
364
#define DF_CS_REMAP3A_V4D2 (df_reg_def_t){ .drd_gens = DF_REV_4D2, \
usr/src/uts/intel/sys/amdzen/df.h
367
#define DF_CS_REMAP3B_V4D2 (df_reg_def_t){ .drd_gens = DF_REV_4D2, \
usr/src/uts/intel/sys/amdzen/df.h
370
#define DF_CS_REMAP3C_V4D2 (df_reg_def_t){ .drd_gens = DF_REV_4D2, \
usr/src/uts/intel/sys/amdzen/df.h
379
#define DF_CFG_ADDR_CTL_V2 (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \
usr/src/uts/intel/sys/amdzen/df.h
383
#define DF_CFG_ADDR_CTL_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \
usr/src/uts/intel/sys/amdzen/df.h
394
#define DF_CFGMAP_V2(x) (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \
usr/src/uts/intel/sys/amdzen/df.h
412
#define DF_CFGMAP_BASE_V4(x) (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \
usr/src/uts/intel/sys/amdzen/df.h
416
#define DF_CFGMAP_LIMIT_V4(x) (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \
usr/src/uts/intel/sys/amdzen/df.h
434
#define DF_IO_BASE_V2(x) (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \
usr/src/uts/intel/sys/amdzen/df.h
438
#define DF_IO_BASE_V4(x) (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \
usr/src/uts/intel/sys/amdzen/df.h
463
#define DF_IO_LIMIT_V2(x) (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \
usr/src/uts/intel/sys/amdzen/df.h
467
#define DF_IO_LIMIT_V4(x) (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \
usr/src/uts/intel/sys/amdzen/df.h
494
#define DF_DRAM_HOLE_V2 (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \
usr/src/uts/intel/sys/amdzen/df.h
498
#define DF_DRAM_HOLE_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \
usr/src/uts/intel/sys/amdzen/df.h
518
#define DF_DRAM_BASE_V2(r) (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \
usr/src/uts/intel/sys/amdzen/df.h
559
#define DF_DRAM_LIMIT_V2(r) (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \
usr/src/uts/intel/sys/amdzen/df.h
586
#define DF_DRAM_BASE_V4(x) (df_reg_def_t){ .drd_gens = DF_REV_4, \
usr/src/uts/intel/sys/amdzen/df.h
590
#define DF_DRAM_BASE_V4D2(x) (df_reg_def_t){ .drd_gens = DF_REV_4D2, \
usr/src/uts/intel/sys/amdzen/df.h
596
#define DF_DRAM_LIMIT_V4(x) (df_reg_def_t){ .drd_gens = DF_REV_4, \
usr/src/uts/intel/sys/amdzen/df.h
600
#define DF_DRAM_LIMIT_V4D2(x) (df_reg_def_t){ .drd_gens = DF_REV_4D2, \
usr/src/uts/intel/sys/amdzen/df.h
608
#define DF_DRAM_CTL_V4(x) (df_reg_def_t){ .drd_gens = DF_REV_4, \
usr/src/uts/intel/sys/amdzen/df.h
612
#define DF_DRAM_CTL_V4D2(x) (df_reg_def_t){ .drd_gens = DF_REV_4D2, \
usr/src/uts/intel/sys/amdzen/df.h
635
#define DF_DRAM_ILV_V4(x) (df_reg_def_t){ .drd_gens = DF_REV_4, \
usr/src/uts/intel/sys/amdzen/df.h
639
#define DF_DRAM_ILV_V4D2(x) (df_reg_def_t){ .drd_gens = DF_REV_4D2, \
usr/src/uts/intel/sys/amdzen/df.h
706
#define DF_DRAM_OFFSET_V2 (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \
usr/src/uts/intel/sys/amdzen/df.h
710
#define DF_DRAM_OFFSET_V4(r) (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \
usr/src/uts/intel/sys/amdzen/df.h
724
#define DF_VGA_EN_V2 (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \
usr/src/uts/intel/sys/amdzen/df.h
728
#define DF_VGA_EN_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \
usr/src/uts/intel/sys/amdzen/df.h
745
#define DF_ECAM_BASE_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \
usr/src/uts/intel/sys/amdzen/df.h
749
#define DF_ECAM_BASE_EXT_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \
usr/src/uts/intel/sys/amdzen/df.h
753
#define DF_ECAM_LIMIT_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \
usr/src/uts/intel/sys/amdzen/df.h
757
#define DF_ECAM_LIMIT_EXT_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \
usr/src/uts/intel/sys/amdzen/df.h
775
#define DF_MMIO_BASE_V2(x) (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \
usr/src/uts/intel/sys/amdzen/df.h
779
#define DF_MMIO_LIMIT_V2(x) (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \
usr/src/uts/intel/sys/amdzen/df.h
783
#define DF_MMIO_BASE_V4(x) (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \
usr/src/uts/intel/sys/amdzen/df.h
787
#define DF_MMIO_LIMIT_V4(x) (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \
usr/src/uts/intel/sys/amdzen/df.h
795
#define DF_MMIO_CTL_V2(x) (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \
usr/src/uts/intel/sys/amdzen/df.h
799
#define DF_MMIO_CTL_V4(x) (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \
usr/src/uts/intel/sys/amdzen/df.h
833
#define DF_MMIO_EXT_V4(x) (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \
usr/src/uts/intel/sys/amdzen/df.h
848
#define DF_GLOB_CTL_V3 (df_reg_def_t){ .drd_gens = DF_REV_ALL_3, \
usr/src/uts/intel/sys/amdzen/df.h
868
#define DF_SYSCFG_V2 (df_reg_def_t){ .drd_gens = DF_REV_2, \
usr/src/uts/intel/sys/amdzen/df.h
884
#define DF_SYSCFG_V3 (df_reg_def_t){ .drd_gens = DF_REV_3, \
usr/src/uts/intel/sys/amdzen/df.h
895
#define DF_SYSCFG_V3P5 (df_reg_def_t){ .drd_gens = DF_REV_3P5, \
usr/src/uts/intel/sys/amdzen/df.h
905
#define DF_SYSCFG_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \
usr/src/uts/intel/sys/amdzen/df.h
919
#define DF_COMPCNT_V2 (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \
usr/src/uts/intel/sys/amdzen/df.h
927
#define DF_COMPCNT_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \
usr/src/uts/intel/sys/amdzen/df.h
946
#define DF_FIDMASK_V2 (df_reg_def_t){ .drd_gens = DF_REV_2, \
usr/src/uts/intel/sys/amdzen/df.h
961
#define DF_FIDMASK0_V3 (df_reg_def_t){ .drd_gens = DF_REV_3, \
usr/src/uts/intel/sys/amdzen/df.h
967
#define DF_FIDMASK1_V3 (df_reg_def_t){ .drd_gens = DF_REV_3, \
usr/src/uts/intel/sys/amdzen/df.h
980
#define DF_FIDMASK0_V3P5 (df_reg_def_t){ .drd_gens = DF_REV_3P5, \
usr/src/uts/intel/sys/amdzen/df.h
984
#define DF_FIDMASK0_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \
usr/src/uts/intel/sys/amdzen/df.h
990
#define DF_FIDMASK1_V3P5 (df_reg_def_t){ .drd_gens = DF_REV_3P5, \
usr/src/uts/intel/sys/amdzen/df.h
994
#define DF_FIDMASK1_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \