devhandle_t
devhandle_t dev_hdl = 0;
extern int px_lib_dev_init(dev_info_t *dip, devhandle_t *dev_hdl);
devhandle_t px_dev_hdl; /* device handle */
static uint64_t msiq_suspend(devhandle_t dev_hdl, pxu_t *pxu_p);
static void msiq_resume(devhandle_t dev_hdl, pxu_t *pxu_p);
hvio_iommu_map(devhandle_t dev_hdl, pxu_t *pxu_p, tsbid_t tsbid, pages_t pages,
hvio_iommu_demap(devhandle_t dev_hdl, pxu_t *pxu_p, tsbid_t tsbid,
hvio_iommu_getmap(devhandle_t dev_hdl, pxu_t *pxu_p, tsbid_t tsbid,
hvio_iommu_getbypass(devhandle_t dev_hdl, pxu_t *pxu_p, r_addr_t ra,
hvio_intr_devino_to_sysino(devhandle_t dev_hdl, pxu_t *pxu_p, devino_t devino,
hvio_intr_getvalid(devhandle_t dev_hdl, sysino_t sysino,
hvio_intr_setvalid(devhandle_t dev_hdl, sysino_t sysino,
hvio_intr_getstate(devhandle_t dev_hdl, sysino_t sysino,
hvio_intr_setstate(devhandle_t dev_hdl, sysino_t sysino,
hvio_intr_gettarget(devhandle_t dev_hdl, pxu_t *pxu_p, sysino_t sysino,
hvio_intr_settarget(devhandle_t dev_hdl, pxu_t *pxu_p, sysino_t sysino,
hvio_msiq_init(devhandle_t dev_hdl, pxu_t *pxu_p)
hvio_msiq_getvalid(devhandle_t dev_hdl, msiqid_t msiq_id,
hvio_msiq_setvalid(devhandle_t dev_hdl, msiqid_t msiq_id,
hvio_msiq_getstate(devhandle_t dev_hdl, msiqid_t msiq_id,
hvio_msiq_setstate(devhandle_t dev_hdl, msiqid_t msiq_id,
hvio_msiq_gethead(devhandle_t dev_hdl, msiqid_t msiq_id,
hvio_msiq_sethead(devhandle_t dev_hdl, msiqid_t msiq_id,
hvio_msiq_gettail(devhandle_t dev_hdl, msiqid_t msiq_id,
hvio_msi_init(devhandle_t dev_hdl, uint64_t addr32, uint64_t addr64)
hvio_msi_getmsiq(devhandle_t dev_hdl, msinum_t msi_num,
hvio_msi_setmsiq(devhandle_t dev_hdl, msinum_t msi_num,
hvio_msi_getvalid(devhandle_t dev_hdl, msinum_t msi_num,
hvio_msi_setvalid(devhandle_t dev_hdl, msinum_t msi_num,
hvio_msi_getstate(devhandle_t dev_hdl, msinum_t msi_num,
hvio_msi_setstate(devhandle_t dev_hdl, msinum_t msi_num,
hvio_msg_getmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type,
hvio_msg_setmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type,
hvio_msg_getvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type,
hvio_msg_setvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type,
hvio_suspend(devhandle_t dev_hdl, pxu_t *pxu_p)
hvio_resume(devhandle_t dev_hdl, devino_t devino, pxu_t *pxu_p)
hvio_cb_suspend(devhandle_t dev_hdl, pxu_t *pxu_p)
hvio_cb_resume(devhandle_t pci_dev_hdl, devhandle_t xbus_dev_hdl,
msiq_suspend(devhandle_t dev_hdl, pxu_t *pxu_p)
msiq_resume(devhandle_t dev_hdl, pxu_t *pxu_p)
devhandle_t dev_hdl, xbus_dev_hdl;
dev_hdl = (devhandle_t)pxu_p->px_address[PX_REG_CSR];
xbus_dev_hdl = (devhandle_t)pxu_p->px_address[PX_REG_XBC];
devhandle_t dev_hdl, xbus_dev_hdl;
dev_hdl = (devhandle_t)pxu_p->px_address[PX_REG_CSR];
xbus_dev_hdl = (devhandle_t)pxu_p->px_address[PX_REG_XBC];
px_lib_dev_init(dev_info_t *dip, devhandle_t *dev_hdl)
*dev_hdl = (devhandle_t)csr_base;
extern uint64_t hvio_intr_devino_to_sysino(devhandle_t dev_hdl, pxu_t *pxu_p,
extern uint64_t hvio_intr_getvalid(devhandle_t dev_hdl, sysino_t sysino,
extern uint64_t hvio_intr_setvalid(devhandle_t dev_hdl, sysino_t sysino,
extern uint64_t hvio_intr_getstate(devhandle_t dev_hdl, sysino_t sysino,
extern uint64_t hvio_intr_setstate(devhandle_t dev_hdl, sysino_t sysino,
extern uint64_t hvio_intr_gettarget(devhandle_t dev_hdl, pxu_t *pxu_p,
extern uint64_t hvio_intr_settarget(devhandle_t dev_hdl, pxu_t *pxu_p,
extern uint64_t hvio_iommu_map(devhandle_t dev_hdl, pxu_t *pxu_p, tsbid_t tsbid,
extern uint64_t hvio_iommu_demap(devhandle_t dev_hdl, pxu_t *pxu_p,
extern uint64_t hvio_iommu_getmap(devhandle_t dev_hdl, pxu_t *pxu_p,
extern uint64_t hvio_iommu_getbypass(devhandle_t dev_hdl, pxu_t *pxu_p,
extern uint64_t hvio_msiq_init(devhandle_t dev_hdl, pxu_t *pxu_p);
extern uint64_t hvio_msiq_getvalid(devhandle_t dev_hdl, msiqid_t msiq_id,
extern uint64_t hvio_msiq_setvalid(devhandle_t dev_hdl, msiqid_t msiq_id,
extern uint64_t hvio_msiq_getstate(devhandle_t dev_hdl, msiqid_t msiq_id,
extern uint64_t hvio_msiq_setstate(devhandle_t dev_hdl, msiqid_t msiq_id,
extern uint64_t hvio_msiq_gethead(devhandle_t dev_hdl, msiqid_t msiq_id,
extern uint64_t hvio_msiq_sethead(devhandle_t dev_hdl, msiqid_t msiq_id,
extern uint64_t hvio_msiq_gettail(devhandle_t dev_hdl, msiqid_t msiq_id,
extern uint64_t hvio_msi_init(devhandle_t dev_hdl, uint64_t addr32,
extern uint64_t hvio_msi_getmsiq(devhandle_t dev_hdl, msinum_t msi_num,
extern uint64_t hvio_msi_setmsiq(devhandle_t dev_hdl, msinum_t msi_num,
extern uint64_t hvio_msi_getvalid(devhandle_t dev_hdl, msinum_t msi_num,
extern uint64_t hvio_msi_setvalid(devhandle_t dev_hdl, msinum_t msi_num,
extern uint64_t hvio_msi_getstate(devhandle_t dev_hdl, msinum_t msi_num,
extern uint64_t hvio_msi_setstate(devhandle_t dev_hdl, msinum_t msi_num,
extern uint64_t hvio_msg_getmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type,
extern uint64_t hvio_msg_setmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type,
extern uint64_t hvio_msg_getvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type,
extern uint64_t hvio_msg_setvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type,
extern uint64_t hvio_suspend(devhandle_t dev_hdl, pxu_t *pxu_p);
extern void hvio_resume(devhandle_t dev_hdl,
extern uint64_t hvio_cb_suspend(devhandle_t dev_hdl, pxu_t *pxu_p);
extern void hvio_cb_resume(devhandle_t pci_dev_hdl, devhandle_t xbus_dev_hdl,
devhandle_t dev_hdl;
dev_hdl = (devhandle_t)((rp->phys_addr >> 32) & DEVHDLE_MASK);
devhandle_t dev_hdl = (devhandle_t)handle;
extern int fpc_get_fire_perfreg(devhandle_t dev_hdl, int regid, uint64_t *data);
extern int fpc_set_fire_perfreg(devhandle_t dev_hdl, int regid, uint64_t data);
*dev_hdl = (devhandle_t)((rp->phys_addr >> 32) & DEVHDLE_MASK);
devhandle_t hdl = DIP_TO_HANDLE(dip); /* need to cache hdl */
px_lib_dev_init(dev_info_t *dip, devhandle_t *dev_hdl)
extern uint64_t hvio_iommu_map(devhandle_t dev_hdl, tsbid_t tsbid,
extern uint64_t hvio_iommu_demap(devhandle_t dev_hdl, tsbid_t tsbid,
extern uint64_t hvio_iommu_getmap(devhandle_t dev_hdl, tsbid_t tsbid,
extern uint64_t hvio_iommu_getbypass(devhandle_t dev_hdl, r_addr_t ra,
extern uint64_t hvio_dma_sync(devhandle_t dev_hdl, r_addr_t ra,
extern uint64_t hvio_msiq_conf(devhandle_t dev_hdl, msiqid_t msiq_id,
extern uint64_t hvio_msiq_info(devhandle_t dev_hdl, msiqid_t msiq_id,
extern uint64_t hvio_msiq_getvalid(devhandle_t dev_hdl, msiqid_t msiq_id,
extern uint64_t hvio_msiq_setvalid(devhandle_t dev_hdl, msiqid_t msiq_id,
extern uint64_t hvio_msiq_getstate(devhandle_t dev_hdl, msiqid_t msiq_id,
extern uint64_t hvio_msiq_setstate(devhandle_t dev_hdl, msiqid_t msiq_id,
extern uint64_t hvio_msiq_gethead(devhandle_t dev_hdl, msiqid_t msiq_id,
extern uint64_t hvio_msiq_sethead(devhandle_t dev_hdl, msiqid_t msiq_id,
extern uint64_t hvio_msiq_gettail(devhandle_t dev_hdl, msiqid_t msiq_id,
extern uint64_t hvio_msi_getmsiq(devhandle_t dev_hdl, msinum_t msi_num,
extern uint64_t hvio_msi_setmsiq(devhandle_t dev_hdl, msinum_t msi_num,
extern uint64_t hvio_msi_getvalid(devhandle_t dev_hdl, msinum_t msi_num,
extern uint64_t hvio_msi_setvalid(devhandle_t dev_hdl, msinum_t msi_num,
extern uint64_t hvio_msi_getstate(devhandle_t dev_hdl, msinum_t msi_num,
extern uint64_t hvio_msi_setstate(devhandle_t dev_hdl, msinum_t msi_num,
extern uint64_t pci_error_send(devhandle_t dev_hdl, devino_t devino,
extern uint64_t hvio_msg_getmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type,
extern uint64_t hvio_msg_setmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type,
extern uint64_t hvio_msg_getvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type,
extern uint64_t hvio_msg_setvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type,
extern uint64_t hvio_peek(devhandle_t dev_hdl, r_addr_t ra, size_t size,
extern uint64_t hvio_poke(devhandle_t dev_hdl, r_addr_t ra, size_t size,
extern uint64_t hvio_get_rp_mps_cap(devhandle_t dev_hdl, pci_device_t bdf,
extern uint64_t hvio_set_rp_mps(devhandle_t dev_hdl, pci_device_t bdf,
extern uint64_t pci_iov_root_configured(devhandle_t dev_hdl);
static uint64_t hvio_rp_mps(devhandle_t dev_hdl, pci_device_t bdf, int32_t *mps,
hvio_get_rp_mps_cap(devhandle_t dev_hdl, pci_device_t bdf, int32_t *mps_cap)
hvio_set_rp_mps(devhandle_t dev_hdl, pci_device_t bdf, int32_t mps)
hvio_rp_mps(devhandle_t dev_hdl, pci_device_t bdf, int32_t *mps, int op)
extern uint64_t hvio_config_get(devhandle_t, pci_device_t, pci_config_offset_t,
extern uint64_t hvio_config_put(devhandle_t, pci_device_t, pci_config_offset_t,