cmi_hdl_wrmsr
(void) cmi_hdl_wrmsr(hdl, AMD_MSR_NB_MISC, nval);
if (cmi_hdl_wrmsr(hdl, msr, val) == CMI_SUCCESS)
(void) cmi_hdl_wrmsr(hdl, MSR_AMD_HWCR, hwcr);
(void) cmi_hdl_wrmsr(hdl, MSR_AMD_HWCR, hwcr);
if (cmi_hdl_wrmsr(hdl, msr, val) == CMI_SUCCESS)
(void) cmi_hdl_wrmsr(hdl, MSR_AMD_HWCR, hwcr);
(void) cmi_hdl_wrmsr(hdl, MSR_AMD_HWCR, hwcr);
(void) cmi_hdl_wrmsr(hdl, MC_MSR_NB_MISC(i),
if (cmi_hdl_wrmsr(hdl, ppin_ctl_msr, MSR_PPIN_CTL_ENABLED) !=
if (cmi_hdl_wrmsr(hdl, ppin_ctl_msr, MSR_PPIN_CTL_DISABLED) ==
(void) cmi_hdl_wrmsr(hdl, ppin_ctl_msr, MSR_PPIN_CTL_LOCKED);
(void) cmi_hdl_wrmsr(hdl, IA32_MSR_MC_CTL2(i), ctl2);
(void) cmi_hdl_wrmsr(hdl, IA32_MSR_MC_CTL2(i), ctl2);
(void) cmi_hdl_wrmsr(hdl, IA32_MSR_MC(i, CTL),
(void) cmi_hdl_wrmsr(hdl, IA32_MSR_MC(i, STATUS),
(void) cmi_hdl_wrmsr(hdl, IA32_MSR_MCG_STATUS, 0ULL);
(void) cmi_hdl_wrmsr(hdl, IA32_MSR_MCG_CTL,
(void) cmi_hdl_wrmsr(hdl,
(void) cmi_hdl_wrmsr(hdl, IA32_MSR_MC_CTL2(bank),
(void) cmi_hdl_wrmsr(hdl, IA32_MSR_MC(i, STATUS), 0ULL);
(void) cmi_hdl_wrmsr(hdl,
(void) cmi_hdl_wrmsr(hdl,
(void) cmi_hdl_wrmsr(hdl, IA32_MSR_MCG_STATUS, 0);
errs += (cmi_hdl_wrmsr(hdl, msr, val) != CMI_SUCCESS);
(void) cmi_hdl_wrmsr(hdl, IA32_MSR_MC_CTL2(i),
(void) cmi_hdl_wrmsr(hdl,
extern cmi_errno_t cmi_hdl_wrmsr(cmi_hdl_t, uint_t, uint64_t);