usr/src/uts/i86pc/cpu/amd_opteron/ao_main.c

70

if (cmi_hdl_rdmsr(hdl, IA32_MSR_MCG_CAP, &cap) != CMI_SUCCESS)

usr/src/uts/i86pc/cpu/amd_opteron/ao_mca.c

303

if (cmi_hdl_rdmsr(hdl, AMD_MSR_NB_MISC, &val) != CMI_SUCCESS)

usr/src/uts/i86pc/cpu/amd_opteron/ao_mca.c

827

if (cmi_hdl_rdmsr(hdl, MSR_AMD_HWCR, &hwcr) != CMI_SUCCESS)

usr/src/uts/i86pc/cpu/amd_opteron/ao_mca.c

871

(void) cmi_hdl_rdmsr(hdl, ao_bank_cfgs[i].bank_ctl_mask,

usr/src/uts/i86pc/cpu/authenticamd/authamd_main.c

252

if (cmi_hdl_rdmsr(hdl, MSR_AMD_HWCR, &hwcr) != CMI_SUCCESS)

usr/src/uts/i86pc/cpu/authenticamd/authamd_main.c

499

if (cmi_hdl_rdmsr(hdl, IA32_MSR_MCG_CAP, &cap) != CMI_SUCCESS)

usr/src/uts/i86pc/cpu/authenticamd/authamd_main.c

705

if (cmi_hdl_rdmsr(hdl, MC_MSR_NB_MISC(i),

usr/src/uts/i86pc/cpu/generic_cpu/gcpu_main.c

113

if (cmi_hdl_rdmsr(hdl, ppin_ctl_msr, &value) != CMI_SUCCESS) {

usr/src/uts/i86pc/cpu/generic_cpu/gcpu_main.c

135

if (cmi_hdl_rdmsr(hdl, ppin_ctl_msr, &value) != CMI_SUCCESS) {

usr/src/uts/i86pc/cpu/generic_cpu/gcpu_main.c

144

if (cmi_hdl_rdmsr(hdl, ppin_msr, &value) != CMI_SUCCESS) {

usr/src/uts/i86pc/cpu/generic_cpu/gcpu_mca.c

1153

if (cmi_hdl_rdmsr(hdl, IA32_MSR_MCG_CAP, &cap) != CMI_SUCCESS)

usr/src/uts/i86pc/cpu/generic_cpu/gcpu_mca.c

1182

(void) cmi_hdl_rdmsr(hdl, IA32_MSR_MCG_CTL,

usr/src/uts/i86pc/cpu/generic_cpu/gcpu_mca.c

1319

(void) cmi_hdl_rdmsr(hdl, IA32_MSR_MC_CTL2(i), &ctl2);

usr/src/uts/i86pc/cpu/generic_cpu/gcpu_mca.c

1324

(void) cmi_hdl_rdmsr(hdl, IA32_MSR_MC_CTL2(i), &ctl2);

usr/src/uts/i86pc/cpu/generic_cpu/gcpu_mca.c

1389

(void) cmi_hdl_rdmsr(hdl, IA32_MSR_MC(i, CTL),

usr/src/uts/i86pc/cpu/generic_cpu/gcpu_mca.c

1392

(void) cmi_hdl_rdmsr(hdl, IA32_MSR_MC(i, STATUS),

usr/src/uts/i86pc/cpu/generic_cpu/gcpu_mca.c

1397

(void) cmi_hdl_rdmsr(hdl, IA32_MSR_MC(i, ADDR),

usr/src/uts/i86pc/cpu/generic_cpu/gcpu_mca.c

1629

(void) cmi_hdl_rdmsr(hdl,

usr/src/uts/i86pc/cpu/generic_cpu/gcpu_mca.c

1670

(void) cmi_hdl_rdmsr(hdl, IA32_MSR_MC_CTL2(bank),

usr/src/uts/i86pc/cpu/generic_cpu/gcpu_mca.c

1804

if (cmi_hdl_rdmsr(hdl, IA32_MSR_MCG_STATUS, &mcg_status) !=

usr/src/uts/i86pc/cpu/generic_cpu/gcpu_mca.c

1805

CMI_SUCCESS || cmi_hdl_rdmsr(hdl, IA32_MSR_MCG_CAP, &cap) !=

usr/src/uts/i86pc/cpu/generic_cpu/gcpu_mca.c

1857

if (cmi_hdl_rdmsr(hdl, IA32_MSR_MC(i, STATUS), &status) !=

usr/src/uts/i86pc/cpu/generic_cpu/gcpu_mca.c

1879

(void) cmi_hdl_rdmsr(hdl, IA32_MSR_MC(i, ADDR), &addr);

usr/src/uts/i86pc/cpu/generic_cpu/gcpu_mca.c

1882

(void) cmi_hdl_rdmsr(hdl, IA32_MSR_MC(i, MISC), &misc);

usr/src/uts/i86pc/cpu/generic_cpu/gcpu_mca.c

1905

if (ispoll && (err = cmi_hdl_rdmsr(hdl, IA32_MSR_MC(i, STATUS),

usr/src/uts/i86pc/cpu/generic_cpu/gcpu_mca.c

2010

if (cmi_hdl_rdmsr(hdl, IA32_MSR_MCG_STATUS, &mcg_status) !=

usr/src/uts/i86pc/cpu/generic_cpu/gcpu_poll_ntv.c

105

(void) cmi_hdl_rdmsr(hdl, IA32_MSR_MC_CTL2(i),

usr/src/uts/intel/sys/cpu_module.h

151

extern cmi_errno_t cmi_hdl_rdmsr(cmi_hdl_t, uint_t, uint64_t *);