usr/src/cmd/pcieadm/pcieadm_cfgspace.c

3054

if (bitx32(tphcap, 10, 9) != 1) {

usr/src/cmd/pcieadm/pcieadm_cfgspace.c

3058

nents = bitx32(tphcap, 26, 16) + 1;

usr/src/cmd/pcieadm/pcieadm_cfgspace.c

3566

if (bitx32(cap, 5, 5) == 0) {

usr/src/cmd/pcieadm/pcieadm_cfgspace.c

3578

uint32_t nwords = bitx32(cap, 11, 8);

usr/src/cmd/pcieadm/pcieadm_cfgspace.c

3580

if (bitx32(cap, 5, 5) == 0 || nwords < 4) {

usr/src/cmd/pcieadm/pcieadm_cfgspace.c

3592

uint32_t nwords = bitx32(cap, 11, 8);

usr/src/cmd/pcieadm/pcieadm_cfgspace.c

3594

if (bitx32(cap, 5, 5) == 0 || nwords < 5) {

usr/src/cmd/pcieadm/pcieadm_cfgspace.c

3606

int32_t nwords = (int32_t)bitx32(cap, 11, 8);

usr/src/cmd/pcieadm/pcieadm_cfgspace.c

3608

if (nwords == 0 || bitx32(cap, 5, 5) == 0) {

usr/src/cmd/pcieadm/pcieadm_cfgspace.c

3752

uint32_t nents = bitx32(cap, 2, 0) + 1;

usr/src/cmd/pcieadm/pcieadm_cfgspace.c

4450

uint32_t caplo = bitx32(base, 31, 29);

usr/src/cmd/pcieadm/pcieadm_cfgspace.c

4458

uint32_t capid = bitx32(base, 31, 27);

usr/src/cmd/pcieadm/pcieadm_cfgspace.c

4475

bitx32(base, 31, 27));

usr/src/cmd/pcieadm/pcieadm_cfgspace.c

4850

if (bitx32(ap_cap, 8, 8) == 0)

usr/src/cmd/ucodeadm/ucodeadm.c

199

const uint8_t xfamily = bitx32(sig, 27, 20);

usr/src/cmd/ucodeadm/ucodeadm.c

200

const uint8_t bfamily = bitx32(sig, 11, 8);

usr/src/cmd/ucodeadm/ucodeadm.c

201

const uint8_t xmodel = bitx32(sig, 19, 16);

usr/src/cmd/ucodeadm/ucodeadm.c

202

const uint8_t bmodel = bitx32(sig, 7, 4);

usr/src/cmd/ucodeadm/ucodeadm.c

207

*stepping = bitx32(sig, 3, 0);

usr/src/cmd/ucodeadm/ucodeadm.c

298

month = bcd_to_int(bitx32(patch->uh_date, 31, 24));

usr/src/cmd/ucodeadm/ucodeadm.c

299

day = bcd_to_int(bitx32(patch->uh_date, 23, 16));

usr/src/cmd/ucodeadm/ucodeadm.c

300

yearl = bcd_to_int(bitx32(patch->uh_date, 7, 0));

usr/src/common/mc/zen_umc/zen_umc_decode.c

1866

run ^= bitx32(in, i, i);

usr/src/uts/common/io/i2c/ctrl/ismt/ismt.h

101

#define ISMT_R_MSTS_GET_MIS(r) bitx32(r, 5, 5)

usr/src/uts/common/io/i2c/ctrl/ismt/ismt.h

102

#define ISMT_R_MSTS_GET_MEIS(r) bitx32(r, 4, 4)

usr/src/uts/common/io/i2c/ctrl/ismt/ismt.h

103

#define ISMT_R_MSTS_GET_IP(r) bitx32(r, 0, 0)

usr/src/uts/common/io/i2c/ctrl/ismt/ismt.h

123

#define ISMT_R_SPGT_GET_SPD(r) bitx32(r, 31, 30)

usr/src/uts/common/io/i2c/ctrl/ismt/ismt.h

128

#define ISMT_R_SPGT_GET_THDDAT(r) bitx32(r, 19, 16)

usr/src/uts/common/io/i2c/ctrl/ismt/ismt.h

129

#define ISMT_R_SPGT_GET_TSUDAT(r) bitx32(r, 11, 8)

usr/src/uts/common/io/i2c/ctrl/ismt/ismt.h

130

#define ISMT_R_SPGT_GET_DG(r) bitx32(r, 7, 0)

usr/src/uts/common/io/i2c/ctrl/ismt/ismt.h

132

#define ISMT_R_SPMT_GET_THIGH(r) bitx32(r, 31, 24)

usr/src/uts/common/io/i2c/ctrl/ismt/ismt.h

133

#define ISMT_R_SPMT_GET_TLOW(r) bitx32(r, 23, 16)

usr/src/uts/common/io/i2c/ctrl/ismt/ismt.h

134

#define ISMT_R_SPMT_GET_THDSTA(r) bitx32(r, 15, 12)

usr/src/uts/common/io/i2c/ctrl/ismt/ismt.h

135

#define ISMT_R_SPMT_GET_TSUSTA(r) bitx32(r, 11, 8)

usr/src/uts/common/io/i2c/ctrl/ismt/ismt.h

136

#define ISMT_R_SPMT_GET_TBUF(r) bitx32(r, 7, 4)

usr/src/uts/common/io/i2c/ctrl/ismt/ismt.h

137

#define ISMT_R_SPMT_GET_TSUSTO(r) bitx32(r, 3, 0)

usr/src/uts/common/io/i2c/ctrl/ismt/ismt.h

170

#define ISMT_DESC_STS_GET_WRLEN(r) bitx32(r, 31, 24)

usr/src/uts/common/io/i2c/ctrl/ismt/ismt.h

171

#define ISMT_DESC_STS_GET_RDLEN(r) bitx32(r, 23, 16)

usr/src/uts/common/io/i2c/ctrl/ismt/ismt.h

172

#define ISMT_DESC_STS_GET_COLRTRY(r) bitx32(r, 14, 12)

usr/src/uts/common/io/i2c/ctrl/ismt/ismt.h

173

#define ISMT_DESC_STS_GET_RETRY(r) bitx32(r, 11, 8)

usr/src/uts/common/io/i2c/ctrl/ismt/ismt.h

174

#define ISMT_DESC_STS_GET_LPR(r) bitx32(r, 7, 7)

usr/src/uts/common/io/i2c/ctrl/ismt/ismt.h

175

#define ISMT_DESC_STS_GET_COL(r) bitx32(r, 6, 6)

usr/src/uts/common/io/i2c/ctrl/ismt/ismt.h

176

#define ISMT_DESC_STS_GET_CLTO(r) bitx32(r, 5, 5)

usr/src/uts/common/io/i2c/ctrl/ismt/ismt.h

177

#define ISMT_DESC_STS_GET_CRC(r) bitx32(r, 4, 4)

usr/src/uts/common/io/i2c/ctrl/ismt/ismt.h

178

#define ISMT_DESC_STS_GET_NACK(r) bitx32(r, 3, 3)

usr/src/uts/common/io/i2c/ctrl/ismt/ismt.h

179

#define ISMT_DESC_STS_GET_SCS(r) bitx32(r, 0, 0)

usr/src/uts/common/io/i2c/ctrl/ismt/ismt.h

72

#define ISMT_R_ERRINFO_GET_INFO2(r) bitx32(r, 15, 13)

usr/src/uts/common/io/i2c/ctrl/ismt/ismt.h

73

#define ISMT_R_ERRINFO_GET_PTRO2(r) bitx32(r, 12, 8)

usr/src/uts/common/io/i2c/ctrl/ismt/ismt.h

74

#define ISMT_R_ERRINFO_GET_INFO1(r) bitx32(r, 7, 5)

usr/src/uts/common/io/i2c/ctrl/ismt/ismt.h

75

#define ISMT_R_ERRINFO_GET_PTRO1(r) bitx32(r, 4, 0)

usr/src/uts/common/io/i2c/ctrl/ismt/ismt.h

92

#define ISMT_R_MCTRL_GET_SPDDIS(r, v) bitx32(r, 3, 3)

usr/src/uts/common/io/i2c/ctrl/ismt/ismt.h

99

#define ISMT_R_MSTS_GET_HMTP(r) bitx32(r, 23, 16)

usr/src/uts/common/io/i2c/ctrl/pchsmbus/pchsmbus.h

59

#define PCH_R_HCFG_GET_SSRESET(r) bitx32(r, 3, 3)

usr/src/uts/common/io/igc/igc.c

1093

return (bitx32(reg, 3 + off, off));

usr/src/uts/common/io/igc/igc.c

1107

return (bitx32(reg, off, off));

usr/src/uts/common/io/nvme/nvme.c

3244

format_nvm.b.fm_lbaf = bitx32(ioc->nif_lbaf, 3, 0);

usr/src/uts/common/io/nvme/nvme.c

3245

format_nvm.b.fm_ses = bitx32(ioc->nif_ses, 2, 0);

usr/src/uts/common/io/nvme/nvme.c

3318

dw10.b.lp_lid = bitx32(log->nigl_lid, 7, 0);

usr/src/uts/common/io/nvme/nvme.c

3319

dw10.b.lp_lsp = bitx32(log->nigl_lsp, 6, 0);

usr/src/uts/common/io/nvme/nvme.c

3320

dw10.b.lp_rae = bitx32(log->nigl_lsp, 0, 0);

usr/src/uts/common/io/nvme/nvme.c

3321

dw10.b.lp_lnumdl = bitx32(ndw, 15, 0);

usr/src/uts/common/io/nvme/nvme.c

3323

dw11.b.lp_numdu = bitx32(ndw, 31, 16);

usr/src/uts/common/io/nvme/nvme.c

3324

dw11.b.lp_lsi = bitx32(log->nigl_lsi, 15, 0);

usr/src/uts/common/io/nvme/nvme.c

3329

dw14.b.lp_csi = bitx32(log->nigl_csi, 7, 0);

usr/src/uts/common/io/nvme/nvme.c

3445

dw10.b.id_cns = bitx32(ioc->nid_cns, 7, 0);

usr/src/uts/common/io/nvme/nvme.c

3446

dw10.b.id_cntid = bitx32(ioc->nid_ctrlid, 15, 0);

usr/src/uts/common/io/nvme/nvme.c

7015

gf_dw10.b.gt_fid = bitx32(feat.nigf_fid, 7, 0);

usr/src/uts/common/io/nvme/nvme.c

7016

gf_dw10.b.gt_sel = bitx32(feat.nigf_sel, 2, 0);

usr/src/uts/common/io/nvme/nvme.c

7355

idns->id_nmic.nm_shared = bitx32(create.nnc_nmic, 0, 0);

usr/src/uts/common/io/scsi/adapters/lmrc/lmrc_reg.h

66

#define LMRC_FW_RESET_REQUIRED(reg) (bitx32((reg), 0, 0) != 0)

usr/src/uts/common/io/scsi/adapters/lmrc/lmrc_reg.h

67

#define LMRC_FW_RESET_ADAPTER(reg) (bitx32((reg), 1, 1) != 0)

usr/src/uts/common/io/scsi/adapters/lmrc/lmrc_reg.h

68

#define LMRC_FW_MAX_CMD(reg) bitx32((reg), 15, 0)

usr/src/uts/common/io/scsi/adapters/lmrc/lmrc_reg.h

69

#define LMRC_FW_MSIX_ENABLED(reg) (bitx32((reg), 26, 26) != 0)

usr/src/uts/common/io/scsi/adapters/lmrc/lmrc_reg.h

70

#define LMRC_FW_STATE(reg) bitx32((reg), 31, 28)

usr/src/uts/common/io/scsi/adapters/lmrc/lmrc_reg.h

73

#define LMRC_MAX_CHAIN_SIZE(reg) bitx32((reg), 9, 5)

usr/src/uts/common/io/scsi/adapters/lmrc/lmrc_reg.h

74

#define LMRC_MAX_REPLY_QUEUES_EXT(reg) bitx32((reg), 21, 14)

usr/src/uts/common/io/scsi/adapters/lmrc/lmrc_reg.h

75

#define LMRC_EXT_CHAIN_SIZE_SUPPORT(reg) (bitx32((reg), 22, 22) != 0)

usr/src/uts/common/io/scsi/adapters/lmrc/lmrc_reg.h

76

#define LMRC_RDPQ_MODE_SUPPORT(reg) (bitx32((reg), 23, 23) != 0)

usr/src/uts/common/io/scsi/adapters/lmrc/lmrc_reg.h

77

#define LMRC_SYNC_CACHE_SUPPORT(reg) (bitx32((reg), 24, 24) != 0)

usr/src/uts/common/io/scsi/adapters/lmrc/lmrc_reg.h

78

#define LMRC_ATOMIC_DESCRIPTOR_SUPPORT(reg) (bitx32((reg), 24, 24) != 0)

usr/src/uts/common/io/scsi/adapters/lmrc/lmrc_reg.h

79

#define LMRC_64BIT_DMA_SUPPORT(reg) (bitx32((reg), 25, 25) != 0)

usr/src/uts/common/io/scsi/adapters/lmrc/lmrc_reg.h

80

#define LMRC_INTR_COALESCING_SUPPORT(reg) (bitx32((reg), 26, 26) != 0)

usr/src/uts/common/io/scsi/adapters/lmrc/lmrc_reg.h

86

#define LMRC_MAX_RAID_MAP_SZ(reg) bitx32((reg), 24, 16)

usr/src/uts/common/io/scsi/adapters/lmrc/lmrc_reg.h

89

#define LMRC_NVME_PAGE_SHIFT(reg) bitx32((reg), 7, 0)

usr/src/uts/common/sys/bitext.h

34

extern uint32_t bitx32(uint32_t, uint_t, uint_t);

usr/src/uts/intel/io/amdzen/amdzen.c

937

if (bitx32(val, 7, 0) != 0) {

usr/src/uts/intel/io/amdzen/amdzen.c

945

if (bitx32(val, 7, 0) != 0) {

usr/src/uts/intel/sys/amdzen/ccd.h

124

#define SMUPWR_CCD_DIE_ID_GET(_r) bitx32(_r, 3, 0)

usr/src/uts/intel/sys/amdzen/ccd.h

158

#define SMUPWR_THREAD_EN_GET_T(_r, _t) bitx32(_r, _t, _t)

usr/src/uts/intel/sys/amdzen/ccd.h

173

#define SMUPWR_THREAD_CFG_GET_SMT_MODE(_r) bitx32(_r, 8, 8)

usr/src/uts/intel/sys/amdzen/ccd.h

176

#define SMUPWR_THREAD_CFG_GET_COMPLEX_COUNT(_r) bitx32(_r, 7, 4)

usr/src/uts/intel/sys/amdzen/ccd.h

177

#define SMUPWR_THREAD_CFG_GET_CORE_COUNT(_r) bitx32(_r, 3, 0)

usr/src/uts/intel/sys/amdzen/ccd.h

190

#define SMUPWR_SOFT_DOWNCORE_GET_DISCORE(_r) bitx32(_r, 7, 0)

usr/src/uts/intel/sys/amdzen/ccd.h

191

#define SMUPWR_SOFT_DOWNCORE_GET_DISCORE_C(_r, _c) bitx32(_r, _c, _c)

usr/src/uts/intel/sys/amdzen/ccd.h

208

#define SMUPWR_CORE_EN_GET(_r) bitx32(_r, 7, 0)

usr/src/uts/intel/sys/amdzen/ccd.h

209

#define SMUPWR_CORE_EN_GET_C(_r, _c) bitx32(_r, _c, _c)

usr/src/uts/intel/sys/amdzen/ccd.h

267

#define L3SOC_THREAD_EN_GET_T(_r, _t) bitx32(_r, _t, _t)

usr/src/uts/intel/sys/amdzen/ccd.h

283

#define L3SOC_THREAD_CFG_GET_SMT_MODE(_r) bitx32(_r, 10, 10)

usr/src/uts/intel/sys/amdzen/ccd.h

286

#define L3SOC_THREAD_CFG_GET_COMPLEX_COUNT(_r) bitx32(_r, 9, 6)

usr/src/uts/intel/sys/amdzen/ccd.h

287

#define L3SOC_THREAD_CFG_GET_CORE_COUNT(_r) bitx32(_r, 3, 0)

usr/src/uts/intel/sys/amdzen/ccd.h

299

#define L3SOC_SOFT_DOWNCORE_GET_DISCORE(_r) bitx32(_r, 15, 0)

usr/src/uts/intel/sys/amdzen/ccd.h

300

#define L3SOC_SOFT_DOWNCORE_GET_DISCORE_C(_r, _c) bitx32(_r, _c, _c)

usr/src/uts/intel/sys/amdzen/ccd.h

314

#define L3SOC_CORE_EN_GET(_r) bitx32(_r, 15, 0)

usr/src/uts/intel/sys/amdzen/ccd.h

315

#define L3SOC_CORE_EN_GET_C(_r, _c) bitx32(_r, _c, _c)

usr/src/uts/intel/sys/amdzen/ccd.h

387

#define SCFCTP_PMREG_INITPKG0_GET_LOG_DIE(_r) bitx32(_r, 22, 19)

usr/src/uts/intel/sys/amdzen/ccd.h

388

#define SCFCTP_PMREG_INITPKG0_GET_LOG_CCX(_r) bitx32(_r, 18, 18)

usr/src/uts/intel/sys/amdzen/ccd.h

389

#define SCFCTP_PMREG_INITPKG0_GET_LOG_CORE(_r) bitx32(_r, 17, 14)

usr/src/uts/intel/sys/amdzen/ccd.h

390

#define SCFCTP_PMREG_INITPKG0_GET_SOCKET(_r) bitx32(_r, 13, 12)

usr/src/uts/intel/sys/amdzen/ccd.h

391

#define SCFCTP_PMREG_INITPKG0_GET_PHYS_DIE(_r) bitx32(_r, 11, 8)

usr/src/uts/intel/sys/amdzen/ccd.h

392

#define SCFCTP_PMREG_INITPKG0_GET_PHYS_CCX(_r) bitx32(_r, 7, 7)

usr/src/uts/intel/sys/amdzen/ccd.h

393

#define SCFCTP_PMREG_INITPKG0_GET_PHYS_CORE(_r) bitx32(_r, 6, 3)

usr/src/uts/intel/sys/amdzen/ccd.h

394

#define SCFCTP_PMREG_INITPKG0_GET_SMTEN(_r) bitx32(_r, 2, 0)

usr/src/uts/intel/sys/amdzen/ccd.h

413

#define SCFCTP_PMREG_INITPKG7_GET_N_SOCKETS(_r) bitx32(_r, 26, 25)

usr/src/uts/intel/sys/amdzen/ccd.h

414

#define SCFCTP_PMREG_INITPKG7_GET_N_DIES(_r) bitx32(_r, 24, 21)

usr/src/uts/intel/sys/amdzen/ccd.h

415

#define SCFCTP_PMREG_INITPKG7_GET_N_CCXS(_r) bitx32(_r, 20, 20)

usr/src/uts/intel/sys/amdzen/ccd.h

416

#define SCFCTP_PMREG_INITPKG7_GET_N_CORES(_r) bitx32(_r, 19, 16)

usr/src/uts/intel/sys/amdzen/ccd.h

417

#define SCFCTP_PMREG_INITPKG7_ZEN4_GET_16TAPIC(_r) bitx32(_r, 11, 11)

usr/src/uts/intel/sys/amdzen/ccd.h

418

#define SCFCTP_PMREG_INITPKG7_GET_CHIDXHASHEN(_r) bitx32(_r, 10, 10)

usr/src/uts/intel/sys/amdzen/ccd.h

419

#define SCFCTP_PMREG_INITPKG7_GET_S3(_r) bitx32(_r, 9, 9)

usr/src/uts/intel/sys/amdzen/ccd.h

420

#define SCFCTP_PMREG_INITPKG7_ZEN3_GET_S0I3(_r) bitx32(_r, 8, 8)

usr/src/uts/intel/sys/amdzen/ccd.h

421

#define SCFCTP_PMREG_INITPKG7_GET_CORETYPEISARM(_r) bitx32(_r, 7, 7)

usr/src/uts/intel/sys/amdzen/ccd.h

422

#define SCFCTP_PMREG_INITPKG7_GET_SOCID(_r) bitx32(_r, 6, 3)

usr/src/uts/intel/sys/amdzen/df.h

1007

#define DF_FIDMASK2_V3P5_GET_SOCK_MASK(r) bitx32(r, 31, 16)

usr/src/uts/intel/sys/amdzen/df.h

1008

#define DF_FIDMASK2_V3P5_GET_DIE_MASK(r) bitx32(r, 15, 0)

usr/src/uts/intel/sys/amdzen/df.h

1027

#define DF_DIEMASK_V2_GET_SOCK_SHIFT(r) bitx32(r, 31, 28)

usr/src/uts/intel/sys/amdzen/df.h

1028

#define DF_DIEMASK_V2_GET_DIE_SHIFT(r) bitx32(r, 27, 24)

usr/src/uts/intel/sys/amdzen/df.h

1029

#define DF_DIEMASK_V2_GET_SOCK_MASK(r) bitx32(r, 23, 16)

usr/src/uts/intel/sys/amdzen/df.h

1030

#define DF_DIEMASK_V2_GET_DIE_MASK(r) bitx32(r, 15, 8)

usr/src/uts/intel/sys/amdzen/df.h

1031

#define DF_DIEMASK_V2_GET_COMP_MASK(r) bitx32(r, 7, 0)

usr/src/uts/intel/sys/amdzen/df.h

1053

#define DF_CCD_EN_V4D2_GET_WIDE_EN(r) bitx32(r, 31, 31)

usr/src/uts/intel/sys/amdzen/df.h

1054

#define DF_CCD_EN_V4_GET_CCX_EN(r) bitx32(r, 17, 16)

usr/src/uts/intel/sys/amdzen/df.h

1055

#define DF_CCD_EN_V4_GET_CCD_EN(r) bitx32(r, 1, 0)

usr/src/uts/intel/sys/amdzen/df.h

1107

#define DF_NP2_CONFIG_V3_GET_SPACE1(r) bitx32(r, 13, 8)

usr/src/uts/intel/sys/amdzen/df.h

1108

#define DF_NP2_CONFIG_V3_GET_SPACE0(r) bitx32(r, 5, 0)

usr/src/uts/intel/sys/amdzen/df.h

1121

#define DF_CCMCFG4_V4_GET_WIDE_EN(r) bitx32(r, 26, 26)

usr/src/uts/intel/sys/amdzen/df.h

1207

#define DF_SYS_FUN_FID1_V3_GET_MSTR_PIE_FID(r) bitx32(r, 21, 16)

usr/src/uts/intel/sys/amdzen/df.h

1208

#define DF_SYS_FUN_FID1_V3_GET_LCL_PIE_FID(r) bitx32(r, 5, 0)

usr/src/uts/intel/sys/amdzen/df.h

1214

#define DF_SYS_FUN_FID1_V4_GET_MSTR_PIE_FID(r) bitx32(r, 27, 16)

usr/src/uts/intel/sys/amdzen/df.h

1215

#define DF_SYS_FUN_FID1_V4D2_GET_MSTR_PIE_FID(r) bitx32(r, 23, 16)

usr/src/uts/intel/sys/amdzen/df.h

1216

#define DF_SYS_FUN_FID1_V4_GET_LCL_PIE_FID(r) bitx32(r, 11, 0)

usr/src/uts/intel/sys/amdzen/df.h

1217

#define DF_SYS_FUN_FID1_V4D2_GET_LCL_PIE_FID(r) bitx32(r, 7, 0)

usr/src/uts/intel/sys/amdzen/df.h

1223

#define DF_SYS_FUN_FID2_V3_GET_FCH_IOMS_FID(r) bitx32(r, 21, 16)

usr/src/uts/intel/sys/amdzen/df.h

1224

#define DF_SYS_FUN_FID2_V3_GET_LCL_IOMS_FID(r) bitx32(r, 5, 0)

usr/src/uts/intel/sys/amdzen/df.h

1230

#define DF_SYS_FUN_FID2_V4_GET_FCH_IOS_FID(r) bitx32(r, 27, 16)

usr/src/uts/intel/sys/amdzen/df.h

1231

#define DF_SYS_FUN_FID2_V4D2_GET_FCH_IOS_FID(r) bitx32(r, 23, 16)

usr/src/uts/intel/sys/amdzen/df.h

134

#define DF_FBICNT_V4_GET_MAJOR(r) bitx32(r, 27, 24)

usr/src/uts/intel/sys/amdzen/df.h

135

#define DF_FBICNT_V4_GET_MINOR(r) bitx32(r, 23, 16)

usr/src/uts/intel/sys/amdzen/df.h

136

#define DF_FBICNT_GET_COUNT(r) bitx32(r, 7, 0)

usr/src/uts/intel/sys/amdzen/df.h

145

#define DF_FBIINFO0_GET_SUBTYPE(r) bitx32(r, 26, 24)

usr/src/uts/intel/sys/amdzen/df.h

187

#define DF_FBIINFO0_GET_HAS_MCA(r) bitx32(r, 23, 23)

usr/src/uts/intel/sys/amdzen/df.h

188

#define DF_FBIINFO0_GET_FTI_DCNT(r) bitx32(r, 21, 20)

usr/src/uts/intel/sys/amdzen/df.h

189

#define DF_FBIINFO0_GET_FTI_PCNT(r) bitx32(r, 18, 16)

usr/src/uts/intel/sys/amdzen/df.h

190

#define DF_FBIINFO0_GET_SDP_RESPCNT(r) bitx32(r, 14, 14)

usr/src/uts/intel/sys/amdzen/df.h

191

#define DF_FBIINFO0_GET_SDP_PCNT(r) bitx32(r, 13, 12)

usr/src/uts/intel/sys/amdzen/df.h

192

#define DF_FBIINFO0_GET_FTI_WIDTH(r) bitx32(r, 9, 8)

usr/src/uts/intel/sys/amdzen/df.h

199

#define DF_FBIINFO0_V3_GET_ENABLED(r) bitx32(r, 6, 6)

usr/src/uts/intel/sys/amdzen/df.h

200

#define DF_FBIINFO0_GET_SDP_WIDTH(r) bitx32(r, 5, 4)

usr/src/uts/intel/sys/amdzen/df.h

207

#define DF_FBIINFO0_GET_TYPE(r) bitx32(r, 3, 0)

usr/src/uts/intel/sys/amdzen/df.h

232

#define DF_FBINFO1_GET_FTI3_NINSTID(r) bitx32(r, 31, 24)

usr/src/uts/intel/sys/amdzen/df.h

233

#define DF_FBINFO1_GET_FTI2_NINSTID(r) bitx32(r, 23, 16)

usr/src/uts/intel/sys/amdzen/df.h

234

#define DF_FBINFO1_GET_FTI1_NINSTID(r) bitx32(r, 15, 8)

usr/src/uts/intel/sys/amdzen/df.h

235

#define DF_FBINFO1_GET_FTI0_NINSTID(r) bitx32(r, 7, 0)

usr/src/uts/intel/sys/amdzen/df.h

244

#define DF_FBINFO2_GET_FTI5_NINSTID(r) bitx32(r, 15, 8)

usr/src/uts/intel/sys/amdzen/df.h

245

#define DF_FBINFO2_GET_FTI4_NINSTID(r) bitx32(r, 7, 0)

usr/src/uts/intel/sys/amdzen/df.h

254

#define DF_FBIINFO3_V2_GET_BLOCKID(r) bitx32(r, 15, 8)

usr/src/uts/intel/sys/amdzen/df.h

255

#define DF_FBIINFO3_V3_GET_BLOCKID(r) bitx32(r, 13, 8)

usr/src/uts/intel/sys/amdzen/df.h

256

#define DF_FBIINFO3_V3P5_GET_BLOCKID(r) bitx32(r, 11, 8)

usr/src/uts/intel/sys/amdzen/df.h

257

#define DF_FBIINFO3_V4_GET_BLOCKID(r) bitx32(r, 19, 8)

usr/src/uts/intel/sys/amdzen/df.h

258

#define DF_FBIINFO3_GET_INSTID(r) bitx32(r, 7, 0)

usr/src/uts/intel/sys/amdzen/df.h

269

#define DF_CAPAB_GET_EXTCSREMAP(r) bitx32(r, 2, 2)

usr/src/uts/intel/sys/amdzen/df.h

270

#define DF_CAPAB_GET_SPF(r) bitx32(r, 1, 1)

usr/src/uts/intel/sys/amdzen/df.h

271

#define DF_CAPAB_GET_POISON(r) bitx32(r, 0, 0)

usr/src/uts/intel/sys/amdzen/df.h

281

#define DF_CS_REMAP_GET_CSX(r, x) bitx32(r, (3 + (4 * (x))), (4 * ((x))))

usr/src/uts/intel/sys/amdzen/df.h

335

#define DF_CS_REMAP_GET_CSX_V4B(r, x) bitx32(r, (4 + (5 * (x))), (5 * ((x))))

usr/src/uts/intel/sys/amdzen/df.h

386

#define DF_CFG_ADDR_CTL_GET_BUS_NUM(r) bitx32(r, 7, 0)

usr/src/uts/intel/sys/amdzen/df.h

399

#define DF_CFGMAP_V2_GET_BUS_LIMIT(r) bitx32(r, 31, 24)

usr/src/uts/intel/sys/amdzen/df.h

400

#define DF_CFGMAP_V2_GET_BUS_BASE(r) bitx32(r, 23, 16)

usr/src/uts/intel/sys/amdzen/df.h

401

#define DF_CFGMAP_V2_GET_DEST_ID(r) bitx32(r, 11, 4)

usr/src/uts/intel/sys/amdzen/df.h

402

#define DF_CFGMAP_V3_GET_DEST_ID(r) bitx32(r, 13, 4)

usr/src/uts/intel/sys/amdzen/df.h

403

#define DF_CFGMAP_V3P5_GET_DEST_ID(r) bitx32(r, 7, 4)

usr/src/uts/intel/sys/amdzen/df.h

404

#define DF_CFGMAP_V2_GET_WE(r) bitx32(r, 1, 1)

usr/src/uts/intel/sys/amdzen/df.h

405

#define DF_CFGMAP_V2_GET_RE(r) bitx32(r, 0, 0)

usr/src/uts/intel/sys/amdzen/df.h

419

#define DF_CFGMAP_BASE_V4_GET_BASE(r) bitx32(r, 23, 16)

usr/src/uts/intel/sys/amdzen/df.h

420

#define DF_CFGMAP_BASE_V4_GET_SEG(r) bitx32(r, 15, 8)

usr/src/uts/intel/sys/amdzen/df.h

421

#define DF_CFGMAP_BASE_V4_GET_WE(r) bitx32(r, 1, 1)

usr/src/uts/intel/sys/amdzen/df.h

422

#define DF_CFGMAP_BASE_V4_GET_RE(r) bitx32(r, 0, 0)

usr/src/uts/intel/sys/amdzen/df.h

423

#define DF_CFGMAP_LIMIT_V4_GET_LIMIT(r) bitx32(r, 23, 16)

usr/src/uts/intel/sys/amdzen/df.h

424

#define DF_CFGMAP_LIMIT_V4_GET_DEST_ID(r) bitx32(r, 11, 0)

usr/src/uts/intel/sys/amdzen/df.h

425

#define DF_CFGMAP_LIMIT_V4D2_GET_DEST_ID(r) bitx32(r, 7, 0)

usr/src/uts/intel/sys/amdzen/df.h

444

#define DF_IO_BASE_V2_GET_BASE(r) bitx32(r, 24, 12)

usr/src/uts/intel/sys/amdzen/df.h

445

#define DF_IO_BASE_V2_GET_IE(r) bitx32(r, 5, 5)

usr/src/uts/intel/sys/amdzen/df.h

446

#define DF_IO_BASE_V2_GET_WE(r) bitx32(r, 1, 1)

usr/src/uts/intel/sys/amdzen/df.h

447

#define DF_IO_BASE_V2_GET_RE(r) bitx32(r, 0, 0)

usr/src/uts/intel/sys/amdzen/df.h

453

#define DF_IO_BASE_V4_GET_BASE(r) bitx32(r, 28, 16)

usr/src/uts/intel/sys/amdzen/df.h

454

#define DF_IO_BASE_V4_GET_IE(r) bitx32(r, 5, 5)

usr/src/uts/intel/sys/amdzen/df.h

455

#define DF_IO_BASE_V4_GET_WE(r) bitx32(r, 1, 1)

usr/src/uts/intel/sys/amdzen/df.h

456

#define DF_IO_BASE_V4_GET_RE(r) bitx32(r, 0, 0)

usr/src/uts/intel/sys/amdzen/df.h

473

#define DF_IO_LIMIT_V2_GET_LIMIT(r) bitx32(r, 24, 12)

usr/src/uts/intel/sys/amdzen/df.h

474

#define DF_IO_LIMIT_V2_GET_DEST_ID(r) bitx32(r, 7, 0)

usr/src/uts/intel/sys/amdzen/df.h

475

#define DF_IO_LIMIT_V3_GET_DEST_ID(r) bitx32(r, 9, 0)

usr/src/uts/intel/sys/amdzen/df.h

476

#define DF_IO_LIMIT_V3P5_GET_DEST_ID(r) bitx32(r, 3, 0)

usr/src/uts/intel/sys/amdzen/df.h

482

#define DF_IO_LIMIT_V4_GET_LIMIT(r) bitx32(r, 28, 16)

usr/src/uts/intel/sys/amdzen/df.h

483

#define DF_IO_LIMIT_V4_GET_DEST_ID(r) bitx32(r, 11, 0)

usr/src/uts/intel/sys/amdzen/df.h

484

#define DF_IO_LIMIT_V4D2_GET_DEST_ID(r) bitx32(r, 7, 0)

usr/src/uts/intel/sys/amdzen/df.h

501

#define DF_DRAM_HOLE_GET_BASE(r) bitx32(r, 31, 24)

usr/src/uts/intel/sys/amdzen/df.h

503

#define DF_DRAM_HOLE_GET_VALID(r) bitx32(r, 0, 0)

usr/src/uts/intel/sys/amdzen/df.h

521

#define DF_DRAM_BASE_V2_GET_BASE(r) bitx32(r, 31, 12)

usr/src/uts/intel/sys/amdzen/df.h

523

#define DF_DRAM_BASE_V2_GET_ILV_ADDR(r) bitx32(r, 10, 8)

usr/src/uts/intel/sys/amdzen/df.h

524

#define DF_DRAM_BASE_V2_GET_ILV_CHAN(r) bitx32(r, 7, 4)

usr/src/uts/intel/sys/amdzen/df.h

533

#define DF_DRAM_BASE_V2_GET_HOLE_EN(r) bitx32(r, 1, 1)

usr/src/uts/intel/sys/amdzen/df.h

534

#define DF_DRAM_BASE_V2_GET_VALID(r) bitx32(r, 0, 0)

usr/src/uts/intel/sys/amdzen/df.h

536

#define DF_DRAM_BASE_V3_GET_ILV_ADDR(r) bitx32(r, 11, 9)

usr/src/uts/intel/sys/amdzen/df.h

537

#define DF_DRAM_BASE_V3_GET_ILV_SOCK(r) bitx32(r, 8, 8)

usr/src/uts/intel/sys/amdzen/df.h

538

#define DF_DRAM_BASE_V3_GET_ILV_DIE(r) bitx32(r, 7, 6)

usr/src/uts/intel/sys/amdzen/df.h

539

#define DF_DRAM_BASE_V3_GET_ILV_CHAN(r) bitx32(r, 5, 2)

usr/src/uts/intel/sys/amdzen/df.h

541

#define DF_DRAM_BASE_V3P5_GET_ILV_ADDR(r) bitx32(r, 11, 9)

usr/src/uts/intel/sys/amdzen/df.h

542

#define DF_DRAM_BASE_V3P5_GET_ILV_SOCK(r) bitx32(r, 8, 8)

usr/src/uts/intel/sys/amdzen/df.h

543

#define DF_DRAM_BASE_V3P5_GET_ILV_DIE(r) bitx32(r, 7, 7)

usr/src/uts/intel/sys/amdzen/df.h

544

#define DF_DRAM_BASE_V3P5_GET_ILV_CHAN(r) bitx32(r, 6, 2)

usr/src/uts/intel/sys/amdzen/df.h

562

#define DF_DRAM_LIMIT_V2_GET_LIMIT(r) bitx32(r, 31, 12)

usr/src/uts/intel/sys/amdzen/df.h

566

#define DF_DRAM_LIMIT_V2_GET_ILV_DIE(r) bitx32(r, 11, 10)

usr/src/uts/intel/sys/amdzen/df.h

567

#define DF_DRAM_LIMIT_V2_GET_ILV_SOCK(r) bitx32(r, 8, 8)

usr/src/uts/intel/sys/amdzen/df.h

568

#define DF_DRAM_LIMIT_V2_GET_DEST_ID(r) bitx32(r, 7, 0)

usr/src/uts/intel/sys/amdzen/df.h

570

#define DF_DRAM_LIMIT_V3_GET_BUS_BREAK(r) bitx32(r, 10, 10)

usr/src/uts/intel/sys/amdzen/df.h

571

#define DF_DRAM_LIMIT_V3_GET_DEST_ID(r) bitx32(r, 9, 0)

usr/src/uts/intel/sys/amdzen/df.h

573

#define DF_DRAM_LIMIT_V3P5_GET_DEST_ID(r) bitx32(r, 3, 0)

usr/src/uts/intel/sys/amdzen/df.h

593

#define DF_DRAM_BASE_V4_GET_ADDR(r) bitx32(r, 27, 0)

usr/src/uts/intel/sys/amdzen/df.h

603

#define DF_DRAM_LIMIT_V4_GET_ADDR(r) bitx32(r, 27, 0)

usr/src/uts/intel/sys/amdzen/df.h

615

#define DF_DRAM_CTL_V4_GET_DEST_ID(r) bitx32(r, 27, 16)

usr/src/uts/intel/sys/amdzen/df.h

616

#define DF_DRAM_CTL_V4D2_GET_DEST_ID(r) bitx32(r, 23, 16)

usr/src/uts/intel/sys/amdzen/df.h

617

#define DF_DRAM_CTL_V4D2_GET_HASH_1T(r) bitx32(r, 15, 15)

usr/src/uts/intel/sys/amdzen/df.h

622

#define DF_DRAM_CTL_V4_GET_COL_SWIZ(r) bitx32(r, 11, 11)

usr/src/uts/intel/sys/amdzen/df.h

623

#define DF_DRAM_CTL_V4_GET_HASH_1G(r) bitx32(r, 10, 10)

usr/src/uts/intel/sys/amdzen/df.h

624

#define DF_DRAM_CTL_V4_GET_HASH_2M(r) bitx32(r, 9, 9)

usr/src/uts/intel/sys/amdzen/df.h

625

#define DF_DRAM_CTL_V4_GET_HASH_64K(r) bitx32(r, 8, 8)

usr/src/uts/intel/sys/amdzen/df.h

626

#define DF_DRAM_CTL_V4D2_GET_HASH_4K(r) bitx32(r, 7, 7)

usr/src/uts/intel/sys/amdzen/df.h

627

#define DF_DRAM_CTL_V4_GET_REMAP_SEL(r) bitx32(r, 7, 5)

usr/src/uts/intel/sys/amdzen/df.h

628

#define DF_DRAM_CTL_V4D2_GET_REMAP_SEL(r) bitx32(r, 6, 5)

usr/src/uts/intel/sys/amdzen/df.h

629

#define DF_DRAM_CTL_V4_GET_REMAP_EN(r) bitx32(r, 4, 4)

usr/src/uts/intel/sys/amdzen/df.h

630

#define DF_DRAM_CTL_V4_GET_SCM(r) bitx32(r, 2, 2)

usr/src/uts/intel/sys/amdzen/df.h

631

#define DF_DRAM_CTL_V4_GET_HOLE_EN(r) bitx32(r, 1, 1)

usr/src/uts/intel/sys/amdzen/df.h

632

#define DF_DRAM_CTL_V4_GET_VALID(r) bitx32(r, 0, 0)

usr/src/uts/intel/sys/amdzen/df.h

642

#define DF_DRAM_ILV_V4_GET_SOCK(r) bitx32(r, 18, 18)

usr/src/uts/intel/sys/amdzen/df.h

643

#define DF_DRAM_ILV_V4_GET_DIE(r) bitx32(r, 13, 12)

usr/src/uts/intel/sys/amdzen/df.h

650

#define DF_DRAM_ILV_V4D2_GET_CHAN(r) bitx32(r, 9, 4)

usr/src/uts/intel/sys/amdzen/df.h

680

#define DF_DRAM_ILV_V4_GET_CHAN(r) bitx32(r, 8, 4)

usr/src/uts/intel/sys/amdzen/df.h

695

#define DF_DRAM_ILV_V4_GET_ADDR(r) bitx32(r, 2, 0)

usr/src/uts/intel/sys/amdzen/df.h

713

#define DF_DRAM_OFFSET_V2_GET_OFFSET(r) bitx32(r, 31, 20)

usr/src/uts/intel/sys/amdzen/df.h

714

#define DF_DRAM_OFFSET_V3_GET_OFFSET(r) bitx32(r, 31, 12)

usr/src/uts/intel/sys/amdzen/df.h

715

#define DF_DRAM_OFFSET_V4_GET_OFFSET(r) bitx32(r, 24, 1)

usr/src/uts/intel/sys/amdzen/df.h

717

#define DF_DRAM_OFFSET_GET_EN(r) bitx32(r, 0, 0)

usr/src/uts/intel/sys/amdzen/df.h

732

#define DF_VGA_EN_GET_FABID(r) bitx32(r, 15, 4)

usr/src/uts/intel/sys/amdzen/df.h

733

#define DF_VGA_EN_GET_CPUDIS(r) bitx32(r, 2, 2)

usr/src/uts/intel/sys/amdzen/df.h

734

#define DF_VGA_EN_GET_NP(r) bitx32(r, 1, 1)

usr/src/uts/intel/sys/amdzen/df.h

735

#define DF_VGA_EN_GET_EN(r) bitx32(r, 0, 0)

usr/src/uts/intel/sys/amdzen/df.h

760

#define DF_ECAM_V4_GET_ADDR(r) bitx32(r, 31, 20)

usr/src/uts/intel/sys/amdzen/df.h

764

#define DF_ECAM_BASE_V4_GET_EN(r) bitx32(r, 0, 0)

usr/src/uts/intel/sys/amdzen/df.h

766

#define DF_ECAM_EXT_V4_GET_ADDR(r) bitx32(r, 23, 0)

usr/src/uts/intel/sys/amdzen/df.h

802

#define DF_MMIO_CTL_V2_GET_NP(r) bitx32(r, 12, 12)

usr/src/uts/intel/sys/amdzen/df.h

803

#define DF_MMIO_CTL_V2_GET_DEST_ID(r) bitx32(r, 11, 4)

usr/src/uts/intel/sys/amdzen/df.h

807

#define DF_MMIO_CTL_V3_GET_NP(r) bitx32(r, 16, 16)

usr/src/uts/intel/sys/amdzen/df.h

808

#define DF_MMIO_CTL_V3_GET_DEST_ID(r) bitx32(r, 13, 4)

usr/src/uts/intel/sys/amdzen/df.h

809

#define DF_MMIO_CTL_V3P5_GET_DEST_ID(r) bitx32(r, 7, 4)

usr/src/uts/intel/sys/amdzen/df.h

814

#define DF_MMIO_CTL_V4_GET_DEST_ID(r) bitx32(r, 27, 16)

usr/src/uts/intel/sys/amdzen/df.h

815

#define DF_MMIO_CTL_V4D2_GET_DEST_ID(r) bitx32(r, 23, 16)

usr/src/uts/intel/sys/amdzen/df.h

816

#define DF_MMIO_CTL_V4_GET_NP(r) bitx32(r, 3, 3)

usr/src/uts/intel/sys/amdzen/df.h

821

#define DF_MMIO_CTL_GET_CPU_DIS(r) bitx32(r, 2, 2)

usr/src/uts/intel/sys/amdzen/df.h

822

#define DF_MMIO_CTL_GET_WE(r) bitx32(r, 1, 1)

usr/src/uts/intel/sys/amdzen/df.h

823

#define DF_MMIO_CTL_GET_RE(r) bitx32(r, 0, 0)

usr/src/uts/intel/sys/amdzen/df.h

836

#define DF_MMIO_EXT_V4_GET_LIMIT(r) bitx32(r, 23, 16)

usr/src/uts/intel/sys/amdzen/df.h

837

#define DF_MMIO_EXT_V4_GET_BASE(r) bitx32(r, 7, 0)

usr/src/uts/intel/sys/amdzen/df.h

851

#define DF_GLOB_CTL_V3_GET_HASH_1G(r) bitx32(r, 22, 22)

usr/src/uts/intel/sys/amdzen/df.h

852

#define DF_GLOB_CTL_V3_GET_HASH_2M(r) bitx32(r, 21, 21)

usr/src/uts/intel/sys/amdzen/df.h

853

#define DF_GLOB_CTL_V3_GET_HASH_64K(r) bitx32(r, 20, 20)

usr/src/uts/intel/sys/amdzen/df.h

871

#define DF_SYSCFG_V2_GET_SOCK_ID(r) bitx32(r, 27, 27)

usr/src/uts/intel/sys/amdzen/df.h

872

#define DF_SYSCFG_V2_GET_DIE_ID(r) bitx32(r, 25, 24)

usr/src/uts/intel/sys/amdzen/df.h

873

#define DF_SYSCFG_V2_GET_MY_TYPE(r) bitx32(r, 22, 21)

usr/src/uts/intel/sys/amdzen/df.h

874

#define DF_SYSCFG_V2_GET_LOCAL_IS_ME(r) bitx32(r, 19, 16)

usr/src/uts/intel/sys/amdzen/df.h

875

#define DF_SYSCFG_V2_GET_LOCAL_TYPE3(r) bitx32(r, 13, 12)

usr/src/uts/intel/sys/amdzen/df.h

876

#define DF_SYSCFG_V2_GET_LOCAL_TYPE2(r) bitx32(r, 11, 10)

usr/src/uts/intel/sys/amdzen/df.h

877

#define DF_SYSCFG_V2_GET_LOCAL_TYPE1(r) bitx32(r, 9, 8)

usr/src/uts/intel/sys/amdzen/df.h

878

#define DF_SYSCFG_V2_GET_LOCAL_TYPE0(r) bitx32(r, 7, 6)

usr/src/uts/intel/sys/amdzen/df.h

879

#define DF_SYSCFG_V2_GET_OTHER_SOCK(r) bitx32(r, 5, 5)

usr/src/uts/intel/sys/amdzen/df.h

880

#define DF_SYSCFG_V2_GET_DIE_PRESENT(r) bitx32(r, 4, 0)

usr/src/uts/intel/sys/amdzen/df.h

881

#define DF_SYSCFG_V2_DIE_PRESENT(x) bitx32(r, 3, 0)

usr/src/uts/intel/sys/amdzen/df.h

887

#define DF_SYSCFG_V3_GET_NODE_ID(r) bitx32(r, 30, 28)

usr/src/uts/intel/sys/amdzen/df.h

888

#define DF_SYSCFG_V3_GET_OTHER_SOCK(r) bitx32(r, 27, 27)

usr/src/uts/intel/sys/amdzen/df.h

889

#define DF_SYSCFG_V3_GET_OTHER_TYPE(r) bitx32(r, 26, 25)

usr/src/uts/intel/sys/amdzen/df.h

890

#define DF_SYSCFG_V3_GET_MY_TYPE(r) bitx32(r, 24, 23)

usr/src/uts/intel/sys/amdzen/df.h

891

#define DF_SYSCFG_V3_GET_DIE_TYPE(r) bitx32(r, 18, 11)

usr/src/uts/intel/sys/amdzen/df.h

892

#define DF_SYSCFG_V3_GET_DIE_PRESENT(r) bitx32(r, 7, 0)

usr/src/uts/intel/sys/amdzen/df.h

898

#define DF_SYSCFG_V3P5_GET_NODE_ID(r) bitx32(r, 19, 16)

usr/src/uts/intel/sys/amdzen/df.h

899

#define DF_SYSCFG_V3P5_GET_OTHER_SOCK(r) bitx32(r, 8, 8)

usr/src/uts/intel/sys/amdzen/df.h

900

#define DF_SYSCFG_V3P5_GET_NODE_MAP(r) bitx32(r, 4, 4)

usr/src/uts/intel/sys/amdzen/df.h

901

#define DF_SYSCFG_V3P5_GET_OTHER_TYPE(r) bitx32(r, 3, 2)

usr/src/uts/intel/sys/amdzen/df.h

902

#define DF_SYSCFG_V3P5_GET_MY_TYPE(r) bitx32(r, 1, 0)

usr/src/uts/intel/sys/amdzen/df.h

908

#define DF_SYSCFG_V4_GET_NODE_ID(r) bitx32(r, 27, 16)

usr/src/uts/intel/sys/amdzen/df.h

909

#define DF_SYSCFG_V4_GET_OTHER_SOCK(r) bitx32(r, 8, 8)

usr/src/uts/intel/sys/amdzen/df.h

910

#define DF_SYSCFG_V4_GET_NODE_MAP(r) bitx32(r, 4, 4)

usr/src/uts/intel/sys/amdzen/df.h

911

#define DF_SYSCFG_V4_GET_OTHER_TYPE(r) bitx32(r, 3, 2)

usr/src/uts/intel/sys/amdzen/df.h

912

#define DF_SYSCFG_V4_GET_MY_TYPE(r) bitx32(r, 1, 0)

usr/src/uts/intel/sys/amdzen/df.h

922

#define DF_COMPCNT_V2_GET_IOMS(r) bitx32(r, 23, 16)

usr/src/uts/intel/sys/amdzen/df.h

923

#define DF_COMPCNT_V2_GET_GCM(r) bitx32(r, 15, 8)

usr/src/uts/intel/sys/amdzen/df.h

924

#define DF_COMPCNT_V2_GET_PIE(r) bitx32(r, 7, 0)

usr/src/uts/intel/sys/amdzen/df.h

930

#define DF_COMPCNT_V4_GET_IOS(r) bitx32(r, 31, 26)

usr/src/uts/intel/sys/amdzen/df.h

931

#define DF_COMPCNT_V4_GET_GCM(r) bitx32(r, 25, 16)

usr/src/uts/intel/sys/amdzen/df.h

932

#define DF_COMPCNT_V4_GET_IOM(r) bitx32(r, 15, 8)

usr/src/uts/intel/sys/amdzen/df.h

933

#define DF_COMPCNT_V4_GET_PIE(r) bitx32(r, 7, 0)

usr/src/uts/intel/sys/amdzen/df.h

949

#define DF_FIDMASK_V2_GET_SOCK_SHIFT(r) bitx32(r, 31, 28)

usr/src/uts/intel/sys/amdzen/df.h

950

#define DF_FIDMASK_V2_GET_DIE_SHIFT(r) bitx32(r, 27, 24)

usr/src/uts/intel/sys/amdzen/df.h

951

#define DF_FIDMASK_V2_GET_SOCK_MASK(r) bitx32(r, 23, 16)

usr/src/uts/intel/sys/amdzen/df.h

952

#define DF_FIDMASK_V2_GET_DIE_MASK(r) bitx32(r, 15, 8)

usr/src/uts/intel/sys/amdzen/df.h

964

#define DF_FIDMASK0_V3_GET_NODE_MASK(r) bitx32(r, 25, 16)

usr/src/uts/intel/sys/amdzen/df.h

965

#define DF_FIDMASK0_V3_GET_COMP_MASK(r) bitx32(r, 9, 0)

usr/src/uts/intel/sys/amdzen/df.h

970

#define DF_FIDMASK1_V3_GET_SOCK_MASK(r) bitx32(r, 26, 24)

usr/src/uts/intel/sys/amdzen/df.h

971

#define DF_FIDMASK1_V3_GET_DIE_MASK(r) bitx32(r, 18, 16)

usr/src/uts/intel/sys/amdzen/df.h

972

#define DF_FIDMASK1_V3_GET_SOCK_SHIFT(r) bitx32(r, 9, 8)

usr/src/uts/intel/sys/amdzen/df.h

973

#define DF_FIDMASK1_V3_GET_NODE_SHIFT(r) bitx32(r, 3, 0)

usr/src/uts/intel/sys/amdzen/df.h

987

#define DF_FIDMASK0_V3P5_GET_NODE_MASK(r) bitx32(r, 31, 16)

usr/src/uts/intel/sys/amdzen/df.h

988

#define DF_FIDMASK0_V3P5_GET_COMP_MASK(r) bitx32(r, 15, 0)

usr/src/uts/intel/sys/amdzen/df.h

997

#define DF_FIDMASK1_V3P5_GET_SOCK_SHIFT(r) bitx32(r, 11, 8)

usr/src/uts/intel/sys/amdzen/df.h

998

#define DF_FIDMASK1_V3P5_GET_NODE_SHIFT(r) bitx32(r, 3, 0)

usr/src/uts/intel/sys/amdzen/thm.h

178

#define THM_DIE_GET_VALID(r) bitx32(r, 11, 11)

usr/src/uts/intel/sys/amdzen/thm.h

179

#define THM_DIE_GET_TEMP(r) bitx32(r, 10, 0)

usr/src/uts/intel/sys/amdzen/thm.h

59

#define THM_CURTEMP_GET_TEMP(r) bitx32(r, 31, 21)

usr/src/uts/intel/sys/amdzen/thm.h

63

#define THM_CURTEMP_GET_MCM(r) bitx32(r, 20, 20)

usr/src/uts/intel/sys/amdzen/thm.h

64

#define THM_CURTEMP_GET_RANGE(r) bitx32(r, 19, 19)

usr/src/uts/intel/sys/amdzen/thm.h

68

#define THM_CURTEMP_GET_SLEW_SEL(r) bitx32(r, 18, 18)

usr/src/uts/intel/sys/amdzen/thm.h

69

#define THM_CURTEMP_GET_TJ_SEL(r) bitx32(r, 17, 16)

usr/src/uts/intel/sys/amdzen/thm.h

73

#define THM_CURTEMP_GET_TIME_DOWN(r) bitx32(r, 12, 8)

usr/src/uts/intel/sys/amdzen/thm.h

74

#define THM_CURTEMP_GET_SLEW_DOWN_EN(r) bitx32(r, 7, 7)

usr/src/uts/intel/sys/amdzen/thm.h

75

#define THM_CURTEMP_GET_MAX_DIFF(r) bitx32(r, 6, 5)

usr/src/uts/intel/sys/amdzen/thm.h

76

#define THM_CURTEMP_GET_TIME_UP(r) bitx32(r, 4, 0)

usr/src/uts/intel/sys/amdzen/umc.h

134

#define UMC_BASE_GET_ADDR(r) bitx32(r, 31, 1)

usr/src/uts/intel/sys/amdzen/umc.h

136

#define UMC_BASE_GET_EN(r) bitx32(r, 0, 0)

usr/src/uts/intel/sys/amdzen/umc.h

158

#define UMC_BASE_EXT_GET_ADDR(r) bitx32(r, 7, 0)

usr/src/uts/intel/sys/amdzen/umc.h

195

#define UMC_MASK_GET_ADDR(r) bitx32(r, 31, 1)

usr/src/uts/intel/sys/amdzen/umc.h

216

#define UMC_MASK_EXT_GET_ADDR(r) bitx32(r, 7, 0)

usr/src/uts/intel/sys/amdzen/umc.h

242

#define UMC_ADDRCFG_GET_NBANK_BITS(r) bitx32(r, 21, 20)

usr/src/uts/intel/sys/amdzen/umc.h

244

#define UMC_ADDRCFG_GET_NCOL_BITS(r) bitx32(r, 19, 16)

usr/src/uts/intel/sys/amdzen/umc.h

246

#define UMC_ADDRCFG_GET_NROW_BITS_LO(r) bitx32(r, 11, 8)

usr/src/uts/intel/sys/amdzen/umc.h

248

#define UMC_ADDRCFG_GET_NBANKGRP_BITS(r) bitx32(r, 3, 2)

usr/src/uts/intel/sys/amdzen/umc.h

250

#define UMC_ADDRCFG_DDR4_GET_NROW_BITS_HI(r) bitx32(r, 15, 12)

usr/src/uts/intel/sys/amdzen/umc.h

251

#define UMC_ADDRCFG_DDR4_GET_NRM_BITS(r) bitx32(r, 5, 4)

usr/src/uts/intel/sys/amdzen/umc.h

252

#define UMC_ADDRCFG_DDR5_GET_CSXOR(r) bitx32(r, 31, 30)

usr/src/uts/intel/sys/amdzen/umc.h

253

#define UMC_ADDRCFG_DDR5_GET_NRM_BITS(r) bitx32(r, 6, 4)

usr/src/uts/intel/sys/amdzen/umc.h

275

#define UMC_ADDRSEL_GET_ROW_LO(r) bitx32(r, 27, 24)

usr/src/uts/intel/sys/amdzen/umc.h

277

#define UMC_ADDRSEL_GET_BANK4(r) bitx32(r, 19, 16)

usr/src/uts/intel/sys/amdzen/umc.h

278

#define UMC_ADDRSEL_GET_BANK3(r) bitx32(r, 15, 12)

usr/src/uts/intel/sys/amdzen/umc.h

279

#define UMC_ADDRSEL_GET_BANK2(r) bitx32(r, 11, 8)

usr/src/uts/intel/sys/amdzen/umc.h

280

#define UMC_ADDRSEL_GET_BANK1(r) bitx32(r, 7, 4)

usr/src/uts/intel/sys/amdzen/umc.h

281

#define UMC_ADDRSEL_GET_BANK0(r) bitx32(r, 3, 0)

usr/src/uts/intel/sys/amdzen/umc.h

284

#define UMC_ADDRSEL_DDR4_GET_ROW_HI(r) bitx32(r, 31, 28)

usr/src/uts/intel/sys/amdzen/umc.h

331

#define UMC_COLSEL_REMAP_GET_COL(r, x) bitx32(r, (3 + (4 * (x))), (4 * ((x))))

usr/src/uts/intel/sys/amdzen/umc.h

360

#define UMC_RMSEL_DDR4_GET_INV_MSBO(r) bitx32(r, 19, 18)

usr/src/uts/intel/sys/amdzen/umc.h

361

#define UMC_RMSEL_DDR4_GET_INV_MSBE(r) bitx32(r, 17, 16)

usr/src/uts/intel/sys/amdzen/umc.h

362

#define UMC_RMSEL_DDR4_GET_RM2(r) bitx32(r, 11, 8)

usr/src/uts/intel/sys/amdzen/umc.h

363

#define UMC_RMSEL_DDR4_GET_RM1(r) bitx32(r, 7, 4)

usr/src/uts/intel/sys/amdzen/umc.h

364

#define UMC_RMSEL_DDR4_GET_RM0(r) bitx32(r, 3, 0)

usr/src/uts/intel/sys/amdzen/umc.h

374

#define UMC_RMSEL_DDR5_GET_INV_MSBS_SEC(r) bitx32(r, 31, 30)

usr/src/uts/intel/sys/amdzen/umc.h

375

#define UMC_RMSEL_DDR5_GET_INV_MSBS(r) bitx32(r, 29, 28)

usr/src/uts/intel/sys/amdzen/umc.h

376

#define UMC_RMSEL_DDR5_GET_SUBCHAN(r) bitx32(r, 19, 16)

usr/src/uts/intel/sys/amdzen/umc.h

378

#define UMC_RMSEL_DDR5_GET_RM3(r) bitx32(r, 15, 12)

usr/src/uts/intel/sys/amdzen/umc.h

379

#define UMC_RMSEL_DDR5_GET_RM2(r) bitx32(r, 11, 8)

usr/src/uts/intel/sys/amdzen/umc.h

380

#define UMC_RMSEL_DDR5_GET_RM1(r) bitx32(r, 7, 4)

usr/src/uts/intel/sys/amdzen/umc.h

381

#define UMC_RMSEL_DDR5_GET_RM0(r) bitx32(r, 3, 0)

usr/src/uts/intel/sys/amdzen/umc.h

402

#define UMC_DIMMCFG_GET_PKG_RALIGN(r) bitx32(r, 10, 10)

usr/src/uts/intel/sys/amdzen/umc.h

403

#define UMC_DIMMCFG_GET_REFRESH_DIS(r) bitx32(r, 9, 9)

usr/src/uts/intel/sys/amdzen/umc.h

404

#define UMC_DIMMCFG_GET_DQ_SWAP_DIS(r) bitx32(r, 8, 8)

usr/src/uts/intel/sys/amdzen/umc.h

405

#define UMC_DIMMCFG_GET_X16(r) bitx32(r, 7, 7)

usr/src/uts/intel/sys/amdzen/umc.h

406

#define UMC_DIMMCFG_GET_X4(r) bitx32(r, 6, 6)

usr/src/uts/intel/sys/amdzen/umc.h

407

#define UMC_DIMMCFG_GET_LRDIMM(r) bitx32(r, 5, 5)

usr/src/uts/intel/sys/amdzen/umc.h

408

#define UMC_DIMMCFG_GET_RDIMM(r) bitx32(r, 4, 4)

usr/src/uts/intel/sys/amdzen/umc.h

409

#define UMC_DIMMCFG_GET_CISCS(r) bitx32(r, 3, 3)

usr/src/uts/intel/sys/amdzen/umc.h

410

#define UMC_DIMMCFG_GET_3DS(r) bitx32(r, 2, 2)

usr/src/uts/intel/sys/amdzen/umc.h

411

#define UMC_DIMMCFG_GET_OUTPUT_INV(r) bitx32(r, 1, 1)

usr/src/uts/intel/sys/amdzen/umc.h

412

#define UMC_DIMMCFG_GET_MRS_MIRROR(r) bitx32(r, 0, 0)

usr/src/uts/intel/sys/amdzen/umc.h

414

#define UMC_DIMMCFG_DDR4_GET_NVDIMMP(r) bitx32(r, 12, 12)

usr/src/uts/intel/sys/amdzen/umc.h

415

#define UMC_DIMMCFG_DDR4_GET_DDR4e(r) bitx32(r, 11, 11)

usr/src/uts/intel/sys/amdzen/umc.h

416

#define UMC_DIMMCFG_DDR5_GET_RALIGN(r) bitx32(r, 13, 12)

usr/src/uts/intel/sys/amdzen/umc.h

417

#define UMC_DIMMCFG_DDR5_GET_ASYM(r) bitx32(r, 11, 11)

usr/src/uts/intel/sys/amdzen/umc.h

440

#define UMC_BANK_HASH_GET_ROW(r) bitx32(r, 31, 14)

usr/src/uts/intel/sys/amdzen/umc.h

441

#define UMC_BANK_HASH_GET_COL(r) bitx32(r, 13, 1)

usr/src/uts/intel/sys/amdzen/umc.h

442

#define UMC_BANK_HASH_GET_EN(r) bitx32(r, 0, 0)

usr/src/uts/intel/sys/amdzen/umc.h

465

#define UMC_RANK_HASH_GET_ADDR(r) bitx32(r, 31, 1)

usr/src/uts/intel/sys/amdzen/umc.h

467

#define UMC_RANK_HASH_GET_EN(r) bitx32(r, 0, 0)

usr/src/uts/intel/sys/amdzen/umc.h

480

#define UMC_RANK_HASH_EXT_GET_ADDR(r) bitx32(r, 7, 0)

usr/src/uts/intel/sys/amdzen/umc.h

503

#define UMC_PC_HASH_GET_ROW(r) bitx32(r, 31, 14)

usr/src/uts/intel/sys/amdzen/umc.h

504

#define UMC_PC_HASH_GET_COL(r) bitx32(r, 13, 1)

usr/src/uts/intel/sys/amdzen/umc.h

505

#define UMC_PC_HASH_GET_EN(r) bitx32(r, 0, 0)

usr/src/uts/intel/sys/amdzen/umc.h

506

#define UMC_PC_HASH2_GET_BANK(r) bitx32(r, 4, 0)

usr/src/uts/intel/sys/amdzen/umc.h

526

#define UMC_CS_HASH_GET_ADDR(r) bitx32(r, 31, 1)

usr/src/uts/intel/sys/amdzen/umc.h

528

#define UMC_CS_HASH_GET_EN(r) bitx32(r, 0, 0)

usr/src/uts/intel/sys/amdzen/umc.h

541

#define UMC_CS_HASH_EXT_GET_ADDR(r) bitx32(r, 7, 0)

usr/src/uts/intel/sys/amdzen/umc.h

555

#define UMC_UMCCFG_GET_READY(r) bitx32(r, 31, 31)

usr/src/uts/intel/sys/amdzen/umc.h

556

#define UMC_UMCCFG_GET_ECC_EN(r) bitx32(r, 12, 12)

usr/src/uts/intel/sys/amdzen/umc.h

557

#define UMC_UMCCFG_GET_BURST_CTL(r) bitx32(r, 11, 10)

usr/src/uts/intel/sys/amdzen/umc.h

558

#define UMC_UMCCFG_GET_BURST_LEN(r) bitx32(r, 9, 8)

usr/src/uts/intel/sys/amdzen/umc.h

559

#define UMC_UMCCFG_GET_DDR_TYPE(r) bitx32(r, 2, 0)

usr/src/uts/intel/sys/amdzen/umc.h

579

#define UMC_DATACTL_GET_ENCR_EN(r) bitx32(r, 8, 8)

usr/src/uts/intel/sys/amdzen/umc.h

580

#define UMC_DATACTL_GET_SCRAM_EN(r) bitx32(r, 0, 0)

usr/src/uts/intel/sys/amdzen/umc.h

582

#define UMC_DATACTL_DDR4_GET_TWEAK(r) bitx32(r, 19, 16)

usr/src/uts/intel/sys/amdzen/umc.h

583

#define UMC_DATACTL_DDR4_GET_VMG2M(r) bitx32(r, 12, 12)

usr/src/uts/intel/sys/amdzen/umc.h

584

#define UMC_DATACTL_DDR4_GET_FORCE_ENCR(r) bitx32(r, 11, 11)

usr/src/uts/intel/sys/amdzen/umc.h

586

#define UMC_DATACTL_DDR5_GET_TWEAK(r) bitx32(r, 16, 16)

usr/src/uts/intel/sys/amdzen/umc.h

587

#define UMC_DATACTL_DDR5_GET_XTS(r) bitx32(r, 14, 14)

usr/src/uts/intel/sys/amdzen/umc.h

588

#define UMC_DATACTL_DDR5_GET_AES256(r) bitx32(r, 13, 13)

usr/src/uts/intel/sys/amdzen/umc.h

599

#define UMC_ECCCTL_GET_RD_EN(r) bitx32(x, 10, 10)

usr/src/uts/intel/sys/amdzen/umc.h

600

#define UMC_ECCCTL_GET_X16(r) bitx32(x, 9, 9)

usr/src/uts/intel/sys/amdzen/umc.h

601

#define UMC_ECCCTL_GET_UC_FATAL(r) bitx32(x, 8, 8)

usr/src/uts/intel/sys/amdzen/umc.h

602

#define UMC_ECCCTL_GET_SYM_SIZE(r) bitx32(x, 7, 7)

usr/src/uts/intel/sys/amdzen/umc.h

603

#define UMC_ECCCTL_GET_BIT_IL(r) bitx32(x, 6, 6)

usr/src/uts/intel/sys/amdzen/umc.h

604

#define UMC_ECCCTL_GET_HIST_EN(r) bitx32(x, 5, 5)

usr/src/uts/intel/sys/amdzen/umc.h

605

#define UMC_ECCCTL_GET_SW_SYM_EN(r) bitx32(x, 4, 4)

usr/src/uts/intel/sys/amdzen/umc.h

606

#define UMC_ECCCTL_GET_WR_EN(r) bitx32(x, 0, 0)

usr/src/uts/intel/sys/amdzen/umc.h

613

#define UMC_ECCCTL_DDR_GET_PI(r) bitx32(r, 13, 13)

usr/src/uts/intel/sys/amdzen/umc.h

614

#define UMC_ECCCTL_DDR_GET_PF_DIS(r) bitx32(r, 12, 12)

usr/src/uts/intel/sys/amdzen/umc.h

615

#define UMC_ECCCTL_DDR_GET_SDP_OVR(r) bitx32(x, 11, 11)

usr/src/uts/intel/sys/amdzen/umc.h

616

#define UMC_ECCCTL_DDR_GET_REPLAY_EN(r) bitx32(x, 1, 1)

usr/src/uts/intel/sys/amdzen/umc.h

618

#define UMC_ECCCTL_DDR5_GET_PIN_RED(r) bitx32(r, 14, 14)

usr/src/uts/intel/sys/amdzen/umc.h

659

#define UMC_DRAMCFG_LPDDR4_GET_WRPST(r) bitx32(r, 17, 17)

usr/src/uts/intel/sys/amdzen/umc.h

660

#define UMC_DRAMCFG_LPDDR4_GET_RDPST(r) bitx32(r, 16, 16)

usr/src/uts/intel/sys/amdzen/umc.h

661

#define UMC_DRAMCFG_DDR4_GET_PARDIS(r) bitx32(r, 14, 14)

usr/src/uts/intel/sys/amdzen/umc.h

662

#define UMC_DRAMCFG_DDR4_GET_CRCDIS(r) bitx32(r, 13, 13)

usr/src/uts/intel/sys/amdzen/umc.h

663

#define UMC_DRAMCFG_DDR4_GET_PRE2T(r) bitx32(r, 12, 12)

usr/src/uts/intel/sys/amdzen/umc.h

664

#define UMC_DRAMCFG_DDR4_GET_GRDNEN(r) bitx32(r, 11, 11)

usr/src/uts/intel/sys/amdzen/umc.h

665

#define UMC_DRAMCFG_DDR4_GET_CMD2T(r) bitx32(r, 10, 10)

usr/src/uts/intel/sys/amdzen/umc.h

666

#define UMC_DRAMCFG_DDR4_GET_BNKGRP(r) bitx32(r, 8, 8)

usr/src/uts/intel/sys/amdzen/umc.h

667

#define UMC_DRAMCFG_DDR4_GET_MEMCLK(r) bitx32(r, 6, 0)

usr/src/uts/intel/sys/amdzen/umc.h

682

#define UMC_DRAMCFG_DDR5_GET_UGTFCLK(r) bitx32(r, 31, 31)

usr/src/uts/intel/sys/amdzen/umc.h

683

#define UMC_DRAMCFG_LPDDR5_GET_RDECCEN(r) bitx32(r, 29, 29)

usr/src/uts/intel/sys/amdzen/umc.h

684

#define UMC_DRAMCFG_LPDDR5_GET_WRECCEN(r) bitx32(r, 28, 28)

usr/src/uts/intel/sys/amdzen/umc.h

685

#define UMC_DRAMCFG_LPDDR5_GET_WCKRATIO(r) bitx32(r, 27, 26)

usr/src/uts/intel/sys/amdzen/umc.h

689

#define UMC_DRAMCFG_LPDDR5_GET_WCKALWAYS(r) bitx32(r, 25, 25)

usr/src/uts/intel/sys/amdzen/umc.h

690

#define UMC_DRAMCFG_LPDDR5_GET_WRPOST(r) bitx32(r, 23, 23)

usr/src/uts/intel/sys/amdzen/umc.h

691

#define UMC_DRAMCFG_LPDDR5_GET_RDPOST(r) bitx32(r, 22, 22)

usr/src/uts/intel/sys/amdzen/umc.h

692

#define UMC_DRAMCFG_DDR5_GET_CMDPARDIS(r) bitx32(r, 21, 21)

usr/src/uts/intel/sys/amdzen/umc.h

693

#define UMC_DRAMCFG_DDR5_GET_WRCRCDIS(r) bitx32(r, 20, 20)

usr/src/uts/intel/sys/amdzen/umc.h

694

#define UMC_DRAMCFG_DDR5_GET_PRE2T(r) bitx32(r, 19, 19)

usr/src/uts/intel/sys/amdzen/umc.h

695

#define UMC_DRAMCFG_DDR5_GET_GRDNEN(r) bitx32(r, 18, 18)

usr/src/uts/intel/sys/amdzen/umc.h

696

#define UMC_DRAMCFG_DDR5_GET_CMD2T(r) bitx32(r, 17, 17)

usr/src/uts/intel/sys/amdzen/umc.h

697

#define UMC_DRAMCFG_DDR5_GET_BNKGRP(r) bitx32(r, 16, 16)

usr/src/uts/intel/sys/amdzen/umc.h

707

#define UMC_DRAMCFG_DDR5_GET_MEMCLK(r) bitx32(r, 15, 0)

usr/src/uts/intel/sys/amdzen/umc.h

718

#define UMC_DRAMCFG_HYB_GET_LP5ECCORD(r) bitx32(r, 26, 26)

usr/src/uts/intel/sys/amdzen/umc.h

719

#define UMC_DRAMCFG_HYB_GET_LP5RDECCEN(r) bitx32(r, 25, 25)

usr/src/uts/intel/sys/amdzen/umc.h

720

#define UMC_DRAMCFG_HYB_GET_LP5WRECCEN(r) bitx32(r, 24, 24)

usr/src/uts/intel/sys/amdzen/umc.h

721

#define UMC_DRAMCFG_HYB_GET_WCLKRATIO(r) bitx32(r, 22, 21)

usr/src/uts/intel/sys/amdzen/umc.h

722

#define UMC_DRAMCFG_HYB_GET_MEMCLK(r) bitx32(r, 7, 0)

usr/src/uts/intel/sys/amdzen/umc.h

752

#define UMC_UMCCAP_GET_CHAN_DIS(r) bitx32(r, 19, 19)

usr/src/uts/intel/sys/amdzen/umc.h

753

#define UMC_UMCCAP_GET_ENC_DIS(r) bitx32(r, 18, 18)

usr/src/uts/intel/sys/amdzen/umc.h

754

#define UMC_UMCCAP_GET_ECC_DIS(r) bitx32(r, 17, 17)

usr/src/uts/intel/sys/amdzen/umc.h

755

#define UMC_UMCCAP_GET_REG_DIS(r) bitx32(r, 16, 16)

usr/src/uts/intel/sys/amdzen/umc.h

757

#define UMC_UMCACAP_HI_GET_CHIPKILL(r) bitx32(r, 31, 31)

usr/src/uts/intel/sys/amdzen/umc.h

758

#define UMC_UMCACAP_HI_GET_ECC_EN(r) bitx32(r, 30, 30)

usr/src/uts/intel/sys/x86_archext.h

1095

bitx32((uint32_t)(x), 31, _X86_CHIPREV_VENDOR_SHIFT)

usr/src/uts/intel/sys/x86_archext.h

1098

bitx32((uint32_t)(x), 23, _X86_CHIPREV_FAMILY_SHIFT)

usr/src/uts/intel/sys/x86_archext.h

1101

bitx32((uint32_t)(x), 15, 0)

usr/src/uts/intel/sys/x86_archext.h

266

#define CPUID_AMD_8X1F_EBX_NVMPL(r) bitx32(r, 15, 12) /* num VM Perm lvl */

usr/src/uts/intel/sys/x86_archext.h

267

#define CPUID_AMD_8X1F_EBX_PAR(r) bitx32(r, 11, 6) /* paddr bit rem */

usr/src/uts/intel/sys/x86_archext.h

268

#define CPUID_AMD_8X1F_EBX_CBIT(r) bitx32(r, 5, 0) /* C-bit loc in PTE */

usr/src/uts/intel/sys/x86_archext.h

287

#define CPUID_AMD_8X21_EBX_MPS(r) bitx32(11, 0) /* MCU Patch size x 16B */

usr/src/uts/intel/sys/x86_archext.h

296

#define CPUID_AMD_8X22_EBX_NPMC_NB(r) bitx32(r, 15, 10) /* # NB PMC */

usr/src/uts/intel/sys/x86_archext.h

297

#define CPUID_AMD_8X22_EBX_LBR_SZ(r) bitx32(r, 9, 4) /* # LBR Stack ents. */

usr/src/uts/intel/sys/x86_archext.h

298

#define CPUID_AMD_8X22_EBX_NPMC_CORE(r) bitx32(r, 3, 0) /* # core PMC */

usr/src/uts/intel/sys/x86_archext.h

305

#define CPUID_AMD_8X23_EBX_MAX_HMK(r) bitx32(r, 15, 0) /* Max HMK IDs */

usr/src/uts/intel/sys/x86_archext.h

321

#define CPUID_AMD_8X26_EAX_ASYM_TOPO(r) bitx32(r, 31, 31)

usr/src/uts/intel/sys/x86_archext.h

322

#define CPUID_AMD_8x26_EAX_HET_CORES(r) bitx32(r, 30, 30)

usr/src/uts/intel/sys/x86_archext.h

323

#define CPUID_AMD_8X26_EAX_EFF_AVAIL(r) bitx32(r, 29, 29)

usr/src/uts/intel/sys/x86_archext.h

324

#define CPUID_AMD_8X26_EAX_APIC_SHIFT(r) bitx32(r, 4, 0)

usr/src/uts/intel/sys/x86_archext.h

326

#define CPUID_AMD_8X26_EBX_CORE_TYPE(r) bitx32(r, 31, 28)

usr/src/uts/intel/sys/x86_archext.h

327

#define CPUID_AMD_8X26_EBX_MODEL_ID(r) bitx32(r, 27, 24)

usr/src/uts/intel/sys/x86_archext.h

328

#define CPUID_AMD_8X26_EBX_PWR_EFF(r) bitx32(r, 23, 16)

usr/src/uts/intel/sys/x86_archext.h

329

#define CPUID_AMD_8X26_EBX_NLOG_PROC(r) bitx32(r, 15, 0)

usr/src/uts/intel/sys/x86_archext.h

331

#define CPUID_AMD_8X26_ECX_TYPE(r) bitx32(r, 15, 8)

usr/src/uts/intel/sys/x86_archext.h

337

#define CPUID_AMD_8X26_ECX_INPUT(r) bitx32(r, 7, 0)