bitset32
sig = bitset32(sig, 27, 20, xfamily); /* ext family */
sig = bitset32(sig, 11, 8, 0xf); /* family */
sig = bitset32(sig, 19, 16, bitx16(model, 7, 4)); /* ext model */
sig = bitset32(sig, 7, 4, bitx16(model, 3, 0)); /* model */
sig = bitset32(sig, 3, 0, stepping);
chan = bitset32(chan, bit, bit, val);
#define ISMT_R_MSTS_SET_HMTP(r, v) bitset32(r, 23, 16, v)
#define ISMT_R_MDS_SET_SIZE(r, v) bitset32(r, 7, 0, v)
#define ISMT_DESC_CMD_SET_SOE(r, v) bitset32(r, 31, 31, v)
#define ISMT_DESC_CMD_SET_INT(r, v) bitset32(r, 30, 30, v)
#define ISMT_DESC_CMD_SET_I2C(r, v) bitset32(r, 29, 29, v)
#define ISMT_DESC_CMD_SET_PEC(r, v) bitset32(r, 28, 28, v)
#define ISMT_DESC_CMD_SET_FAIR(r, v) bitset32(r, 27, 27, v)
#define ISMT_DESC_CMD_SET_BLK(r, v) bitset32(r, 26, 26, v)
#define ISMT_DESC_CMD_SET_CWRL(r, v) bitset32(r, 24, 24, v)
#define ISMT_DESC_CMD_SET_RDLEN(r, v) bitset32(r, 23, 16, v)
#define ISMT_DESC_CMD_SET_WRLEN(r, v) bitset32(r, 15, 8, v)
#define ISMT_DESC_CMD_SET_ADDR(r, v) bitset32(r, 7, 1, v)
#define ISMT_DESC_CMD_SET_RW(r, v) bitset32(r, 0, 0, v)
#define ISMT_R_GCTRL_SET_SRST(r, v) bitset32(r, 6, 6, v)
#define ISMT_R_GCTRL_SET_KILL(r, v) bitset32(r, 3, 3, v)
#define ISMT_R_GCTRL_SET_TRST(r, v) bitset32(r, 2, 2, v)
#define ISMT_R_MCTRL_SET_FMHP(r, v) bitset32(r, 23, 16, v)
#define ISMT_R_MCTRL_SET_MEIE(r, v) bitset32(r, 4, 4, v)
#define ISMT_R_MCTRL_SET_SS(r, v) bitset32(r, 0, 0, v)
#define PCH_R_HTIM_SET_THIGH(r, v) bitset32(r, 31, 24, v)
#define PCH_R_HTIM_SET_TLOW(r, v) bitset32(r, 23, 16, v)
#define PCH_R_HTIM_SET_THDSTA(r, v) bitset32(r, 15, 12, v)
#define PCH_R_HTIM_SET_TSUSTA(r, v) bitset32(r, 11, 8, v)
#define PCH_R_HTIM_SET_TBUF(r, v) bitset32(r, 7, 4, v)
#define PCH_R_HTIM_SET_TSUSTO(r, v) bitset32(r, 3, 0, v)
return (bitset32(reg, 3 + off, off, mode));
return (bitset32(reg, off, off, en));
ivar = bitset32(ivar, bitend, bitoff, val);
#define IGC_RXDCTL_SET_PTHRESH(r, v) bitset32(r, 4, 0, v)
#define IGC_RXDCTL_SET_HTHRESH(r, v) bitset32(r, 12, 8, v)
#define IGC_RXDCTL_SET_WTHRESH(r, v) bitset32(r, 20, 16, v)
#define IGC_TXDCTL_SET_PTHRESH(r, v) bitset32(r, 4, 0, v)
#define IGC_TXDCTL_SET_HTHRESH(r, v) bitset32(r, 13, 8, v)
#define IGC_TXDCTL_SET_WTHRESH(r, v) bitset32(r, 20, 16, v)
extern uint32_t bitset32(uint32_t, uint_t, uint_t, uint32_t);
#define SMUPWR_THREAD_EN_SET_T(_r, _t) bitset32(_r, _t, _t, 1)
#define SMUPWR_SOFT_DOWNCORE_SET_DISCORE(_r, _v) bitset32(_r, 7, 0, _v)
#define SMUPWR_SOFT_DOWNCORE_SET_DISCORE_C(_r, _c) bitset32(_r, _c, _c, 1)
#define SMUPWR_CORE_EN_SET(_r, _v) bitset32(_r, 7, 0, _v)
#define SMUPWR_CORE_EN_SET_C(_r, _c) bitset32(_r, _c, _c, 1)
#define L3SOC_THREAD_EN_SET_T(_r, _t) bitset32(_r, _t, _t, 1)
#define L3SOC_SOFT_DOWNCORE_SET_DISCORE(_r, _v) bitset32(_r, 15, 0, _v)
#define L3SOC_SOFT_DOWNCORE_SET_DISCORE_C(_r, _c) bitset32(_r, _c, _c, 1)
#define L3SOC_CORE_EN_SET(_r, _v) bitset32(_r, 15, 0, _v)
#define L3SOC_CORE_EN_SET_C(_r, _c) bitset32(_r, _c, _c, 1)
#define DF_FICAA_V2_SET_INST(r, v) bitset32(r, 23, 16, v)
#define DF_FICAA_V2_SET_64B(r, v) bitset32(r, 14, 14, v)
#define DF_FICAA_V2_SET_FUNC(r, v) bitset32(r, 13, 11, v)
#define DF_FICAA_V2_SET_REG(r, v) bitset32(r, 10, 2, v)
#define DF_FICAA_V2_SET_TARG_INST(r, v) bitset32(r, 0, 0, v)
#define DF_FICAA_V4_SET_REG(r, v) bitset32(r, 10, 1, v)
#define DF_IO_BASE_V2_SET_BASE(r, v) bitset32(r, 24, 12, v)
#define DF_IO_BASE_V2_SET_IE(r, v) bitset32(r, 5, 5, v)
#define DF_IO_BASE_V2_SET_WE(r, v) bitset32(r, 1, 1, v)
#define DF_IO_BASE_V2_SET_RE(r, v) bitset32(r, 0, 0, v)
#define DF_IO_BASE_V4_SET_BASE(r, v) bitset32(r, 28, 16, v)
#define DF_IO_BASE_V4_SET_IE(r, v) bitset32(r, 5, 5, v)
#define DF_IO_BASE_V4_SET_WE(r, v) bitset32(r, 1, 1, v)
#define DF_IO_BASE_V4_SET_RE(r, v) bitset32(r, 0, 0, v)
#define DF_IO_LIMIT_V2_SET_LIMIT(r, v) bitset32(r, 24, 12, v)
#define DF_IO_LIMIT_V2_SET_DEST_ID(r, v) bitset32(r, 7, 0, v)
#define DF_IO_LIMIT_V3_SET_DEST_ID(r, v) bitset32(r, 9, 0, v)
#define DF_IO_LIMIT_V3P5_SET_DEST_ID(r, v) bitset32(r, 3, 0, v)
#define DF_IO_LIMIT_V4_SET_LIMIT(r, v) bitset32(r, 28, 16, v)
#define DF_IO_LIMIT_V4_SET_DEST_ID(r, v) bitset32(r, 11, 0, v)
#define DF_IO_LIMIT_V4D2_SET_DEST_ID(r, v) bitset32(r, 7, 0, v)
#define DF_ECAM_V4_SET_ADDR(r, v) bitset32(r, 31, 20, v)
#define DF_ECAM_BASE_V4_SET_EN(r, v) bitset32(r, 0, 0, v)
#define DF_ECAM_EXT_V4_SET_ADDR(r, v) bitset32(r, 23, 0, v)
#define DF_MMIO_CTL_V2_SET_NP(r, v) bitset32(r, 12, 12, v)
#define DF_MMIO_CTL_V2_SET_DEST_ID(r, v) bitset32(r, 11, 4, v)
#define DF_MMIO_CTL_V3_SET_NP(r, v) bitset32(r, 16, 16, v)
#define DF_MMIO_CTL_V3_SET_DEST_ID(r, v) bitset32(r, 13, 4, v)
#define DF_MMIO_CTL_V3P5_SET_DEST_ID(r, v) bitset32(r, 7, 4, v)
#define DF_MMIO_CTL_V4_SET_DEST_ID(r, v) bitset32(r, 27, 16, v)
#define DF_MMIO_CTL_V4D2_SET_DEST_ID(r, v) bitset32(r, 23, 16, v)
#define DF_MMIO_CTL_V4_SET_NP(r, v) bitset32(r, 3, 3, v)
#define DF_MMIO_CTL_SET_CPU_DIS(r, v) bitset32(r, 2, 2, v)
#define DF_MMIO_CTL_SET_WE(r, v) bitset32(r, 1, 1, v)
#define DF_MMIO_CTL_SET_RE(r, v) bitset32(r, 0, 0, v)
#define DF_MMIO_EXT_V4_SET_LIMIT(r, v) bitset32(r, 23, 16, v)
#define DF_MMIO_EXT_V4_SET_BASE(r, v) bitset32(r, 7, 0, v)