bitdef_t
get_bits8(bits8_t v, bitdef_t d)
set_bits8(bits8_t *v, bitdef_t d, uint8_t val)
get_bits16(bits16_t v, bitdef_t d)
set_bits16(bits16_t *v, bitdef_t d, uint16_t val)
get_bits32(bits32_t v, bitdef_t d)
set_bits32(bits32_t *v, bitdef_t d, uint32_t val)
get_bits24(bits24_t v, bitdef_t d)
set_bits24(bits24_t *v, bitdef_t d, uint32_t val)
get_bits64(bits64_t v, bitdef_t d)
set_bits64(bits64_t *v, bitdef_t d, uint64_t val)
#define MLXCX_EVENT_PORT_NUM (bitdef_t){ .bit_shift = 4, .bit_mask = 0xF0 }
#define MLXCX_ETH_CAP_RSS_IND_TBL_CAP (bitdef_t){8, 0x00000f00}
#define MLXCX_ETH_CAP_WQE_INLINE_MODE (bitdef_t){12, 0x00003000}
#define MLXCX_ETH_CAP_MULTI_PKT_SEND_WQE (bitdef_t){14, 0x0000c000}
#define MLXCX_ETH_CAP_MAX_LSO_CAP (bitdef_t){16, 0x001f0000}
#define MLXCX_ETH_CAP_LRO_MAX_MSG_SZ_MODE (bitdef_t){25, 0x06000000}
#define MLXCX_VPORT_ADMIN_STATE (bitdef_t){4, 0xF0}
#define MLXCX_VPORT_OPER_STATE (bitdef_t){0, 0x0F}
#define MLXCX_CMD_MODIFY_RQ_STATE (bitdef_t){ \
#define MLXCX_CMD_MODIFY_SQ_STATE (bitdef_t){ \
#define MLXCX_CQE_RX_HASH_IP_SRC (bitdef_t){0, 0x3}
#define MLXCX_CQE_RX_HASH_IP_DEST (bitdef_t){2, (0x3 << 2)}
#define MLXCX_CQE_RX_HASH_L4_SRC (bitdef_t){4, (0x3 << 4)}
#define MLXCX_CQE_RX_HASH_L4_DEST (bitdef_t){6, (0x3 << 6)}
#define MLXCX_MLCR_LED_TYPE (bitdef_t){ 0, 0x0F }
#define MLXCX_PPLM_CAP_56G (bitdef_t){ 16, 0x000f0000 }
#define MLXCX_PPLM_CAP_100G (bitdef_t){ 12, 0x0000f000 }
#define MLXCX_PPLM_CAP_50G (bitdef_t){ 8, 0x00000f00 }
#define MLXCX_PPLM_CAP_25G (bitdef_t){ 4, 0x000000f0 }
#define MLXCX_PPLM_CAP_10_40G (bitdef_t){ 0, 0x0000000f }
#define MLXCX_SQE_FENCE_MODE (bitdef_t){5, 0xe0}
#define MLXCX_SQE_COMPLETION_MODE (bitdef_t){2, 0x0c}
#define MLXCX_SQE_ETH_INLINE_HDR_SZ (bitdef_t){0, 0x03ff}
#define MLXCX_CQ_ARM_CI (bitdef_t){ .bit_shift = 0, \
#define MLXCX_CQ_ARM_SEQ (bitdef_t){ .bit_shift = 28, \
#define MLXCX_EQ_LOG_PAGE_SIZE (bitdef_t){ .bit_shift = 24, \
#define MLXCX_CQ_CTX_STATUS (bitdef_t){28, 0xf0000000}
#define MLXCX_CQ_CTX_CQE_SZ (bitdef_t){21, 0x00e00000}
#define MLXCX_CQ_CTX_PERIOD_MODE (bitdef_t){15, 0x00018000}
#define MLXCX_CQ_CTX_MINI_CQE_FORMAT (bitdef_t){12, 0x00003000}
#define MLXCX_CQ_CTX_STATE (bitdef_t){8, 0x00000f00}
#define MLXCX_WORKQ_CTX_TYPE (bitdef_t){ \
#define MLXCX_WORKQ_CTX_END_PADDING (bitdef_t){ \
#define MLXCX_RQ_MEM_RQ_TYPE (bitdef_t){ \
#define MLXCX_RQ_STATE (bitdef_t){ \
#define MLXCX_SQ_MIN_WQE_INLINE (bitdef_t){ \
#define MLXCX_SQ_STATE (bitdef_t){ \
#define MLXCX_VPORT_CTX_MIN_WQE_INLINE (bitdef_t){56, 0x0700000000000000}
#define MLXCX_FLOW_HDR_FIRST_VID (bitdef_t){0, 0x07ff}
#define MLXCX_FLOW_HDR_FIRST_PRIO (bitdef_t){13,0x7000}
#define MLXCX_FLOW_HDR_IP_VERSION (bitdef_t){ \
#define MLXCX_EQ_ARM_EQN (bitdef_t){24, 0xff000000}
#define MLXCX_FLOW_HDR_TCP_FLAGS (bitdef_t){ \
#define MLXCX_EQ_ARM_CI (bitdef_t){0, 0x00ffffff}
#define MLXCX_TIR_CTX_DISP_TYPE (bitdef_t){ 4, 0xf0 }
#define MLXCX_TIR_LRO_TIMEOUT (bitdef_t){ 12, 0x0ffff000 }
#define MLXCX_TIR_LRO_ENABLE_MASK (bitdef_t){ 8, 0x00000f00 }
#define MLXCX_TIR_LRO_MAX_MSG_SZ (bitdef_t){ 0, 0x000000ff }
#define MLXCX_TIR_RX_HASH_FN (bitdef_t){ 4, 0xf0 }
#define MLXCX_RX_HASH_L3_TYPE (bitdef_t){ 31, 0x80000000 }
#define MLXCX_RX_HASH_L4_TYPE (bitdef_t){ 30, 0x40000000 }
#define MLXCX_RX_HASH_FIELDS (bitdef_t){ 0, 0x3fffffff }