bge_reg_get32
regval1 = regval2 = bge_reg_get32(bgep, MI_COMMS_REG);
regval2 = bge_reg_get32(bgep, MI_COMMS_REG);
regval1 = bge_reg_get32(bgep, MI_COMMS_REG);
regval1 = bge_reg_get32(bgep, MI_COMMS_REG);
regval2 = bge_reg_get32(bgep, MI_COMMS_REG);
regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG);
regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG);
*dp = bge_reg_get32(bgep, SERIAL_EEPROM_DATA_REG);
regval = bge_reg_get32(bgep, NVM_FLASH_CMD_REG);
*dp = bge_reg_get32(bgep, NVM_FLASH_READ_REG);
(void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG);
(void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG);
regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG);
regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG);
regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG);
config1 = bge_reg_get32(bgep, NVM_CONFIG1_REG);
regval = bge_reg_get32(bgep, regno);
regval = bge_reg_get32(bgep, regno);
val32 = bge_reg_get32(bgep,
regval = bge_reg_get32(bgep, regno);
regval = bge_reg_get32(bgep, regno);
macmode = regval = bge_reg_get32(bgep, ETHERNET_MAC_MODE_REG);
macmode = regval = bge_reg_get32(bgep, TRANSMIT_MAC_MODE_REG);
macmode = regval = bge_reg_get32(bgep, RECEIVE_MAC_MODE_REG);
val = bge_reg_get32(bgep, VCPU_STATUS_REG);
bge_reg_get32(bgep, MEMORY_ARBITER_MODE_REG) |
tmp = bge_reg_get32(bgep, CPMU_PADRNG_CTL_REG);
bge_reg_get32(bgep, MEMORY_ARBITER_MODE_REG));
tmp = bge_reg_get32(bgep, CPMU_CLCK_ORIDE_REG);
tmp = bge_reg_get32(bgep, SERDES_RX_CONTROL);
sx0 = bge_reg_get32(bgep, NIC_DIAG_SEND_INDEX_REG(0));
regval = bge_reg_get32(bgep, reg);
regval = bge_reg_get32(bgep, reg);
regval = bge_reg_get32(bgep, MISC_CONFIG_REG);
(void) bge_reg_get32(bgep, MISC_CONFIG_REG); /* flush */
stats_mask = bge_reg_get32(bgep, RCV_LP_STATS_ENABLE_MASK_REG);
if (bge_reg_get32(bgep, (BGE_RDMA_LENGTH + (i << 2))) >
regval = bge_reg_get32(bgep, RDMA_CORR_CTRL_REG);
flow = bge_reg_get32(bgep, FLOW_ATTN_REG);
rdma = bge_reg_get32(bgep, READ_DMA_STATUS_REG);
wdma = bge_reg_get32(bgep, WRITE_DMA_STATUS_REG);
tmac = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG);
rmac = bge_reg_get32(bgep, RECEIVE_MAC_STATUS_REG);
rxrs = bge_reg_get32(bgep, RX_RISC_STATE_REG);
emac = bge_reg_get32(bgep, ETHERNET_MAC_STATUS_REG);
msis = bge_reg_get32(bgep, MSI_STATUS_REG);
txrs = bge_reg_get32(bgep, TX_RISC_STATE_REG);
regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG);
regval = bge_reg_get32(bgep, MSI_STATUS_REG);
if ((bge_reg_get32(bgep, STAT_IFHCOUT_UPKGS_REG) +
bge_reg_get32(bgep, STAT_IFHCOUT_MPKGS_REG) +
bge_reg_get32(bgep, STAT_IFHCOUT_BPKGS_REG)) >
regval = bge_reg_get32(bgep, RDMA_CORR_CTRL_REG);
regval = bge_reg_get32(bgep, regno);
regval = bge_reg_get32(bgep, regno);
event = bge_reg_get32(bgep, RX_RISC_EVENT_REG);
event = bge_reg_get32(bgep, RX_RISC_EVENT_REG);
event = bge_reg_get32(bgep, RX_RISC_EVENT_REG);
event = bge_reg_get32(bgep, RX_RISC_EVENT_REG);
uint32_t bge_reg_get32(bge_t *bgep, bge_regno_t regno);
(knp++)->value.ui64 = bge_reg_get32(bgep, BUFFER_MANAGER_STATUS_REG);
(knp++)->value.ui64 = bge_reg_get32(bgep, RCV_INITIATOR_STATUS_REG);
(bge_reg_get32(bgep, EEE_MODE_REG) & 0x80) ?
bge_reg_get32(bgep, STAT_IFHCOUT_OCTETS_REG);
bge_reg_get32(bgep, STAT_ETHER_COLLIS_REG);
bge_reg_get32(bgep, STAT_OUTXON_SENT_REG);
bge_reg_get32(bgep, STAT_OUTXOFF_SENT_REG);
bge_reg_get32(bgep, STAT_DOT3_INTMACTX_ERR_REG);
bge_reg_get32(bgep, STAT_DOT3_SCOLLI_FRAME_REG);
bge_reg_get32(bgep, STAT_DOT3_MCOLLI_FRAME_REG);
bge_reg_get32(bgep, STAT_DOT3_DEFERED_TX_REG);
bge_reg_get32(bgep, STAT_DOT3_EXCE_COLLI_REG);
bge_reg_get32(bgep, STAT_DOT3_LATE_COLLI_REG);
bge_reg_get32(bgep, STAT_IFHCOUT_UPKGS_REG);
bge_reg_get32(bgep, STAT_IFHCOUT_MPKGS_REG);
bge_reg_get32(bgep, STAT_IFHCOUT_BPKGS_REG);
bge_reg_get32(bgep, STAT_IFHCIN_OCTETS_REG);
bge_reg_get32(bgep, STAT_ETHER_FRAGMENT_REG);
bge_reg_get32(bgep, STAT_IFHCIN_UPKGS_REG);
bge_reg_get32(bgep, STAT_IFHCIN_MPKGS_REG);
bge_reg_get32(bgep, STAT_IFHCIN_BPKGS_REG);
bge_reg_get32(bgep, STAT_DOT3_FCS_ERR_REG);
bge_reg_get32(bgep, STAT_DOT3_ALIGN_ERR_REG);
bge_reg_get32(bgep, STAT_XON_PAUSE_RX_REG);
bge_reg_get32(bgep, STAT_XOFF_PAUSE_RX_REG);
bge_reg_get32(bgep, STAT_MAC_CTRL_RX_REG);
bge_reg_get32(bgep, STAT_XOFF_STATE_ENTER_REG);
bge_reg_get32(bgep, STAT_DOT3_FRAME_TOOLONG_REG);
bge_reg_get32(bgep, STAT_ETHER_JABBERS_REG);
bge_reg_get32(bgep, STAT_ETHER_UNDERSIZE_REG);
regval = bge_reg_get32(bgep, CPMU_STATUS_REG);
emac_status = bge_reg_get32(bgep, ETHERNET_MAC_STATUS_REG);
macmode = bge_reg_get32(bgep, ETHERNET_MAC_MODE_REG);
bgep->serdes_lpadv = bge_reg_get32(bgep, RX_1000BASEX_AUTONEG_REG);
tx_status = bge_reg_get32(bgep,
emac_status = bge_reg_get32(bgep,
emac_status = bge_reg_get32(bgep,
regval = bge_reg_get32(bgep, SGMII_STATUS_REG);
(void) bge_reg_get32(bgep, MISC_CONFIG_REG); /* flush */
val = bge_reg_get32(bgep, EEE_MODE_REG);
val = bge_reg_get32(bgep, EEE_MODE_REG);
val = bge_reg_get32(bgep, EEE_MODE_REG);