CMI_SUCCESS
if (cmi_hdl_rdmsr(hdl, IA32_MSR_MCG_CAP, &cap) != CMI_SUCCESS)
if (cmi_hdl_rdmsr(hdl, AMD_MSR_NB_MISC, &val) != CMI_SUCCESS)
CMI_SUCCESS)
if (cmi_hdl_wrmsr(hdl, msr, val) == CMI_SUCCESS)
if (cmi_hdl_rdmsr(hdl, MSR_AMD_HWCR, &hwcr) != CMI_SUCCESS)
if (cmi_hdl_wrmsr(hdl, msr, val) == CMI_SUCCESS)
if (cmi_hdl_rdmsr(hdl, MSR_AMD_HWCR, &hwcr) != CMI_SUCCESS)
if (cmi_hdl_rdmsr(hdl, IA32_MSR_MCG_CAP, &cap) != CMI_SUCCESS)
(uint64_t *)&nbm) != CMI_SUCCESS)
if (cmi_hdl_rdmsr(hdl, ppin_ctl_msr, &value) != CMI_SUCCESS) {
CMI_SUCCESS) {
if (cmi_hdl_rdmsr(hdl, ppin_ctl_msr, &value) != CMI_SUCCESS) {
if (cmi_hdl_rdmsr(hdl, ppin_msr, &value) != CMI_SUCCESS) {
CMI_SUCCESS) {
if (cmi_hdl_rdmsr(hdl, IA32_MSR_MCG_CAP, &cap) != CMI_SUCCESS)
CMI_SUCCESS || cmi_hdl_rdmsr(hdl, IA32_MSR_MCG_CAP, &cap) !=
CMI_SUCCESS) {
CMI_SUCCESS)
&status2)) == CMI_SUCCESS) {
} else if (ispoll && err != CMI_SUCCESS) {
CMI_SUCCESS || !(mcg_status & MCG_STATUS_MCIP))
errs += (cmi_hdl_wrmsr(hdl, msr, val) != CMI_SUCCESS);
return (errs == 0 ? CMI_SUCCESS : CMIERR_UNKNOWN);
return (CMI_SUCCESS);
return (CMI_SUCCESS);
0 ? CMI_SUCCESS : CMIERR_NOTSUP);
return (CMI_SUCCESS);
return (CMI_SUCCESS); /* pretend all is ok */
return (CMI_SUCCESS);
*rcp = CMI_SUCCESS;
*rcp = CMI_SUCCESS;
*rcp = CMI_SUCCESS;
*rcp = CMI_SUCCESS;
return (CMI_SUCCESS);
return (CMI_SUCCESS);
*rcp = CMI_SUCCESS;
*errp = CMI_SUCCESS;
int ret = CMI_SUCCESS;
if (e != CMI_SUCCESS) {
CMI_SUCCESS) {
CMI_SUCCESS) {
if (err != CMI_SUCCESS) {
if (err != CMI_SUCCESS) {
if ((err = cmi_mc_unumtopa(NULL, nvl, &pa)) != CMI_SUCCESS &&
return (CMI_SUCCESS);
if ((err = cmi_mc_register_global(&imc_mc_ops, imc)) != CMI_SUCCESS) {
rt = CMI_SUCCESS;
return (CMI_SUCCESS);
return (CMI_SUCCESS);
return (CMI_SUCCESS);
return (CMI_SUCCESS);
return (CMI_SUCCESS);
rt = CMI_SUCCESS;
CMI_SUCCESS : CMIERR_MC_NOMEMSCRUB);
CMI_SUCCESS : CMIERR_MC_NOMEMSCRUB);
if (rc == CMI_SUCCESS && !mc_sw_scrub_disabled++)
return (CMI_SUCCESS);