and
%type <i> pst opt_pst lbrace rbrace rparen comma nl opt_nl and bor
and:
AND | and NL
| ppattern and ppattern %prec AND
| pattern and pattern %prec AND
--- You may not have both BSD4_2 and BSD2_9 defined for this to work
static asndefT and = {"And", SET, -1, 1, {
{0, &and, 0},
and = "";
fprintf(fp, "%s%#lx", and, *ulp++);
and = ", ";
char *and;
and = "";
fprintf(fp, "%s%#lx", and, *ulp++);
and = ", ";
char *and;
ERROR: Check the compilation options _LA_PROCSTR and
ERROR README: and use -DNEWDB instead.
# and thus only $1 exists (and it's null).
Daemon Daemon and Fsdump:/var/rfindd:/bin/sh
rfindd rfindd * 66 1 Rfind Daemon and Fsdump /var/rfindd /bin/sh
struct instruction *and = ora->def;
pseudo_t src2 = and->src2;
if (and->opcode != OP_AND)
return replace_pseudo(or, arg, and->src1);
and->src2 = value_pseudo(nmask);
i6addr_t *src, *dst, *and, *dmask;
and = (i6addr_t *)&mask->sin6_addr;
dmask->i6[0] = and->i6[0];
dmask->i6[1] = and->i6[1];
dmask->i6[2] = and->i6[2];
dmask->i6[3] = and->i6[3];
dst->i6[0] = src->i6[0] & and->i6[0];
dst->i6[1] = src->i6[1] & and->i6[1];
dst->i6[2] = src->i6[2] & and->i6[2];
dst->i6[3] = src->i6[3] & and->i6[3];
u_32_t hmsk[4], msk[4], ips[4], *and;
and = (u_32_t *)addr->s6_addr;
ips[0] = *and & msk[0];
ips[1] = *(and + 1) & msk[1];
ips[2] = *(and + 2) & msk[2];
ips[3] = *(and + 3) & msk[3];
#warn Use QUEUE_MACRO_DEBUG_TRACE and/or QUEUE_MACRO_DEBUG_TRASH
__asm and ecx, 31 \
__asm and ecx, 31 \
__asm and edx, 0xFFFFFFFE \
__asm and edx, 0xFFFFFFFC \
__asm and eax, 1 \
and tmp1, TSB_SOFTSZ_MASK, tmp1; \
and tsbe, TSB_SOFTSZ_MASK, tmp2; /* tmp2=szc */ \
and tmp2, tmp1, tmp1; /* tsbent = virtpage & mask */ \
and tsbe, TSB_SOFTSZ_MASK, tmp2; /* tmp2=szc */ \
and tmp2, tmp1, tmp1; /* tsbent = virtpage & mask */ \
and hmentoff, HTAG_RID_MASK, hmentoff /* mask off rid */ ;\
and hmentoff, BT_ULMASK, use_shctx /* mask bit index */ ;\
and use_shctx, 0x1, use_shctx \
and old, PSR_PIL, scr2; \
and va, 0xff, va; /* mask out all but the lower 8 bits */
and %g1, 3, %g1; \
and %g5, 3, %g6; \
and %g6, 3, %g6; \
and %g1, DCU_DC + DCU_IC, %g1; \
and %g5, CH_ERR_TSTATE_DC_ON + CH_ERR_TSTATE_IC_ON, %g5; \
and afar, scr3, scr3; \
and scr1, JP_ECACHE_NWAY - 1, scr1; /* mask E$ way bits */ \
and afar, scr2, scr3; /* get set offset */ \
and scr3, scr2, scr3; /* VA<63:23>=0 */ \
and scr2, COREID_MASK, scr2; \
and scr3, scr1, scr3; \
and scr3, scr2, scr3; /* VA<63:23>=0 */ \
and afar, scr3, scr3; \
and index, BT_ULMASK, index; \
and scr1, TSTATE_CWP, scr1; \
and r, 0xfff, r
and r, CPU_MASK, r
and scr1, TTE_SZ_BITS, scr1; /* scr1 = tte_size */ \
and scr3, TTE_SZ2_BITS, scr3; /* scr3 = tte_size2 */ \
and vaddr, scr1, scr2; \
and ttepa, tmp1, tmp1; \
and ttepa, tmp1, tmp1; \
and tmp1, tsbreg, tsbreg; \
and tmp1, tmp3, tmp1 ;\
and tmp2, tmp3, tmp2 ;\
and tmp1, TSB_SOFTSZ_MASK, tmp1 ;\
and tmp2, TSB_SOFTSZ_MASK, tmp2 ;\
and size, TSB_SOFTSZ_MASK, size
and index, BT_ULMASK, index; \
and tte, TTE_SZ_BITS, scr1; /* scr1 = ttesz */ \
and vaddr, scr1, scr2; \
and tsbe, TSB_SOFTSZ_MASK, tmp2 /* tmp2=szc */ ;\
and tmp2, tmp1, tmp1 /* tsbent = virtpage & mask */ ;\