Symbol: amdzen_umc_smn_reg
usr/src/uts/intel/sys/amdzen/umc.h
132
#define UMC_BASE(u, i) amdzen_umc_smn_reg(u, D_UMC_BASE, i)
usr/src/uts/intel/sys/amdzen/umc.h
133
#define UMC_BASE_SEC(u, i) amdzen_umc_smn_reg(u, D_UMC_BASE_SEC, i)
usr/src/uts/intel/sys/amdzen/umc.h
155
#define UMC_BASE_EXT_DDR5(u, i) amdzen_umc_smn_reg(u, D_UMC_BASE_EXT_DDR5, i)
usr/src/uts/intel/sys/amdzen/umc.h
157
amdzen_umc_smn_reg(u, D_UMC_BASE_EXT_SEC_DDR5, i)
usr/src/uts/intel/sys/amdzen/umc.h
191
#define UMC_MASK_DDR4(u, i) amdzen_umc_smn_reg(u, D_UMC_MASK_DDR4, i)
usr/src/uts/intel/sys/amdzen/umc.h
192
#define UMC_MASK_SEC_DDR4(u, i) amdzen_umc_smn_reg(u, D_UMC_MASK_SEC_DDR4, i)
usr/src/uts/intel/sys/amdzen/umc.h
193
#define UMC_MASK_DDR5(u, i) amdzen_umc_smn_reg(u, D_UMC_MASK_DDR5, i)
usr/src/uts/intel/sys/amdzen/umc.h
194
#define UMC_MASK_SEC_DDR5(u, i) amdzen_umc_smn_reg(u, D_UMC_MASK_SEC_DDR5, i)
usr/src/uts/intel/sys/amdzen/umc.h
213
#define UMC_MASK_EXT_DDR5(u, i) amdzen_umc_smn_reg(u, D_UMC_MASK_EXT_DDR5, i)
usr/src/uts/intel/sys/amdzen/umc.h
215
amdzen_umc_smn_reg(u, D_UMC_MASK_EXT_SEC_DDR5, i)
usr/src/uts/intel/sys/amdzen/umc.h
240
#define UMC_ADDRCFG_DDR4(u, i) amdzen_umc_smn_reg(u, D_UMC_ADDRCFG_DDR4, i)
usr/src/uts/intel/sys/amdzen/umc.h
241
#define UMC_ADDRCFG_DDR5(u, i) amdzen_umc_smn_reg(u, D_UMC_ADDRCFG_DDR5, i)
usr/src/uts/intel/sys/amdzen/umc.h
273
#define UMC_ADDRSEL_DDR4(u, i) amdzen_umc_smn_reg(u, D_UMC_ADDRSEL_DDR4, i)
usr/src/uts/intel/sys/amdzen/umc.h
274
#define UMC_ADDRSEL_DDR5(u, i) amdzen_umc_smn_reg(u, D_UMC_ADDRSEL_DDR5, i)
usr/src/uts/intel/sys/amdzen/umc.h
323
amdzen_umc_smn_reg(u, D_UMC_COLSEL_LO_DDR4, i)
usr/src/uts/intel/sys/amdzen/umc.h
325
amdzen_umc_smn_reg(u, D_UMC_COLSEL_HI_DDR4, i)
usr/src/uts/intel/sys/amdzen/umc.h
327
amdzen_umc_smn_reg(u, D_UMC_COLSEL_LO_DDR5, i)
usr/src/uts/intel/sys/amdzen/umc.h
329
amdzen_umc_smn_reg(u, D_UMC_COLSEL_HI_DDR5, i)
usr/src/uts/intel/sys/amdzen/umc.h
357
#define UMC_RMSEL_DDR4(u, i) amdzen_umc_smn_reg(u, D_UMC_RMSEL_DDR4, i)
usr/src/uts/intel/sys/amdzen/umc.h
359
amdzen_umc_smn_reg(u, D_UMC_RMSEL_SEC_DDR4, i)
usr/src/uts/intel/sys/amdzen/umc.h
373
#define UMC_RMSEL_DDR5(u, i) amdzen_umc_smn_reg(u, D_UMC_RMSEL_DDR5, i)
usr/src/uts/intel/sys/amdzen/umc.h
400
#define UMC_DIMMCFG_DDR4(u, i) amdzen_umc_smn_reg(u, D_UMC_DIMMCFG_DDR4, i)
usr/src/uts/intel/sys/amdzen/umc.h
401
#define UMC_DIMMCFG_DDR5(u, i) amdzen_umc_smn_reg(u, D_UMC_DIMMCFG_DDR5, i)
usr/src/uts/intel/sys/amdzen/umc.h
437
amdzen_umc_smn_reg(u, D_UMC_BANK_HASH_DDR4, i)
usr/src/uts/intel/sys/amdzen/umc.h
439
amdzen_umc_smn_reg(u, D_UMC_BANK_HASH_DDR5, i)
usr/src/uts/intel/sys/amdzen/umc.h
462
amdzen_umc_smn_reg(u, D_UMC_RANK_HASH_DDR4, i)
usr/src/uts/intel/sys/amdzen/umc.h
464
amdzen_umc_smn_reg(u, D_UMC_RANK_HASH_DDR5, i)
usr/src/uts/intel/sys/amdzen/umc.h
479
amdzen_umc_smn_reg(u, D_UMC_RANK_HASH_EXT_DDR5, i)
usr/src/uts/intel/sys/amdzen/umc.h
501
#define UMC_PC_HASH_DDR5(u) amdzen_umc_smn_reg(u, D_UMC_PC_HASH_DDR5, 0)
usr/src/uts/intel/sys/amdzen/umc.h
502
#define UMC_PC_HASH2_DDR5(u) amdzen_umc_smn_reg(u, D_UMC_PC_HASH2_DDR5, 0)
usr/src/uts/intel/sys/amdzen/umc.h
524
#define UMC_CS_HASH_DDR4(u, i) amdzen_umc_smn_reg(u, D_UMC_CS_HASH_DDR4, i)
usr/src/uts/intel/sys/amdzen/umc.h
525
#define UMC_CS_HASH_DDR5(u, i) amdzen_umc_smn_reg(u, D_UMC_CS_HASH_DDR5, i)
usr/src/uts/intel/sys/amdzen/umc.h
540
amdzen_umc_smn_reg(u, D_UMC_CS_HASH_EXT_DDR5, i)
usr/src/uts/intel/sys/amdzen/umc.h
554
#define UMC_UMCCFG(u) amdzen_umc_smn_reg(u, D_UMC_UMCCFG, 0)
usr/src/uts/intel/sys/amdzen/umc.h
578
#define UMC_DATACTL(u) amdzen_umc_smn_reg(u, D_UMC_DATACTL, 0)
usr/src/uts/intel/sys/amdzen/umc.h
598
#define UMC_ECCCTL(u) amdzen_umc_smn_reg(u, D_UMC_ECCCTL, 0)
usr/src/uts/intel/sys/amdzen/umc.h
651
#define UMC_DRAMCFG(u, i) amdzen_umc_smn_reg(u, D_UMC_DRAMCFG, i)
usr/src/uts/intel/sys/amdzen/umc.h
751
#define UMC_UMCCAP(u) amdzen_umc_smn_reg(u, D_UMC_UMCCAP, 0)
usr/src/uts/intel/sys/amdzen/umc.h
756
#define UMC_UMCCAP_HI(u) amdzen_umc_smn_reg(u, D_UMC_UMCCAP_HI, 0)