usr/src/uts/intel/io/mc-amd/mcamd_dimmcfg.c

111

2 * (ldimm) + ((cslp)->csl_chan == CH_B) : \

usr/src/uts/intel/io/mc-amd/mcamd_dimmcfg.c

112

2 * (cslp)->csl_slot + ((cslp)->csl_chan == CH_B))

usr/src/uts/intel/io/mc-amd/mcamd_dimmcfg.c

125

{ SKT_ALL, 0, DCFG_ALL, 0, { { CH_A, 0, 0 }, { CH_B, 0, 0 } } },

usr/src/uts/intel/io/mc-amd/mcamd_dimmcfg.c

129

{ SKT_ALL, 1, DCFG_ALL, 0, { { CH_A, 0, 1 }, { CH_B, 0, 1 } } },

usr/src/uts/intel/io/mc-amd/mcamd_dimmcfg.c

133

{ SKT_ALL, 2, DCFG_ALL, 1, { { CH_A, 1, 0 }, { CH_B, 1, 0 } } },

usr/src/uts/intel/io/mc-amd/mcamd_dimmcfg.c

137

{ SKT_ALL, 3, DCFG_ALL, 1, { { CH_A, 1, 1 }, { CH_B, 1, 1 } } },

usr/src/uts/intel/io/mc-amd/mcamd_dimmcfg.c

142

{ SKT_940, 4, DCFG_N, 2, { { CH_A, 2, 0 }, { CH_B, 2, 0 } } },

usr/src/uts/intel/io/mc-amd/mcamd_dimmcfg.c

143

{ SKT_940, 4, DCFG_R4, 0, { { CH_A, 2, 0 }, { CH_B, 2, 0 } } },

usr/src/uts/intel/io/mc-amd/mcamd_dimmcfg.c

148

{ SKT_940, 5, DCFG_N, 2, { { CH_A, 2, 1 }, { CH_B, 2, 1 } } },

usr/src/uts/intel/io/mc-amd/mcamd_dimmcfg.c

149

{ SKT_940, 5, DCFG_R4, 0, { { CH_A, 2, 1 }, { CH_B, 2, 1 } } },

usr/src/uts/intel/io/mc-amd/mcamd_dimmcfg.c

154

{ SKT_940, 6, DCFG_N, 3, { { CH_A, 3, 0 }, { CH_B, 3, 0 } } },

usr/src/uts/intel/io/mc-amd/mcamd_dimmcfg.c

155

{ SKT_940, 6, DCFG_R4, 1, { { CH_A, 3, 0 }, { CH_B, 3, 0 } } },

usr/src/uts/intel/io/mc-amd/mcamd_dimmcfg.c

160

{ SKT_940, 7, DCFG_N, 3, { { CH_A, 3, 1 }, { CH_B, 3, 1 } } },

usr/src/uts/intel/io/mc-amd/mcamd_dimmcfg.c

161

{ SKT_940, 7, DCFG_R4, 1, { { CH_A, 3, 1 }, { CH_B, 3, 1 } } }

usr/src/uts/intel/io/mc-amd/mcamd_dimmcfg.c

192

{ SKT_939, 4, DCFG_N, 2, { { CH_B, 0, 0 } } },

usr/src/uts/intel/io/mc-amd/mcamd_dimmcfg.c

196

{ SKT_939, 5, DCFG_N, 2, { { CH_B, 0, 1 } } },

usr/src/uts/intel/io/mc-amd/mcamd_dimmcfg.c

200

{ SKT_939, 6, DCFG_N, 3, { { CH_B, 1, 0 } } },

usr/src/uts/intel/io/mc-amd/mcamd_dimmcfg.c

204

{ SKT_939, 7, DCFG_N, 3, { { CH_B, 1, 1 } } }

usr/src/uts/intel/io/mc-amd/mcamd_dimmcfg.c

229

{ SKT_NPT, 0, DCFG_ALLNPT, 0, { { CH_A, 0, 0 }, { CH_B, 0, 0 } } },

usr/src/uts/intel/io/mc-amd/mcamd_dimmcfg.c

233

{ SKT_NPT, 1, DCFG_ALLNPT, 0, { { CH_A, 0, 1 }, { CH_B, 0, 1 } } },

usr/src/uts/intel/io/mc-amd/mcamd_dimmcfg.c

237

{ AM2F1207, 2, DCFG_N | DCFG_R4, 1, { { CH_A, 1, 0 }, { CH_B, 1, 0 } } },

usr/src/uts/intel/io/mc-amd/mcamd_dimmcfg.c

238

{ AM2, 2, DCFG_S4, 0, { { CH_A, 1, 0 }, { CH_B, 1, 0 } } },

usr/src/uts/intel/io/mc-amd/mcamd_dimmcfg.c

239

{ S1g1, 2, DCFG_N, 1, { { CH_A, 0, 2 }, { CH_B, 0, 2 } } },

usr/src/uts/intel/io/mc-amd/mcamd_dimmcfg.c

240

{ S1g1, 2, DCFG_S4, 0, { { CH_A, 0, 2 }, { CH_B, 0, 2 } } },

usr/src/uts/intel/io/mc-amd/mcamd_dimmcfg.c

244

{ AM2F1207, 3, DCFG_N | DCFG_R4, 1, { { CH_A, 1, 1 }, { CH_B, 1, 1 } } },

usr/src/uts/intel/io/mc-amd/mcamd_dimmcfg.c

245

{ AM2, 3, DCFG_S4, 0, { { CH_A, 1, 1 }, { CH_B, 1, 1 } } },

usr/src/uts/intel/io/mc-amd/mcamd_dimmcfg.c

246

{ S1g1, 3, DCFG_N, 1, { { CH_A, 0, 3 }, { CH_B, 0, 3 } } },

usr/src/uts/intel/io/mc-amd/mcamd_dimmcfg.c

247

{ S1g1, 3, DCFG_S4, 0, { { CH_A, 0, 3 }, { CH_B, 0, 3 } } },

usr/src/uts/intel/io/mc-amd/mcamd_dimmcfg.c

251

{ F1207, 4, DCFG_N, 2, { { CH_A, 2, 0 }, { CH_B, 2, 0 } } },

usr/src/uts/intel/io/mc-amd/mcamd_dimmcfg.c

252

{ F1207, 4, DCFG_R4, 0, { { CH_A, 2, 0 }, { CH_B, 2, 0 } } },

usr/src/uts/intel/io/mc-amd/mcamd_dimmcfg.c

256

{ F1207, 5, DCFG_N, 2, { { CH_A, 2, 1 }, { CH_B, 2, 1 } } },

usr/src/uts/intel/io/mc-amd/mcamd_dimmcfg.c

257

{ F1207, 5, DCFG_R4, 0, { { CH_A, 2, 1 }, { CH_B, 2, 1 } } },

usr/src/uts/intel/io/mc-amd/mcamd_dimmcfg.c

261

{ F1207, 6, DCFG_N, 3, { { CH_A, 3, 0 }, { CH_B, 3, 0 } } },

usr/src/uts/intel/io/mc-amd/mcamd_dimmcfg.c

262

{ F1207, 6, DCFG_R4, 1, { { CH_A, 3, 0 }, { CH_B, 3, 0 } } },

usr/src/uts/intel/io/mc-amd/mcamd_dimmcfg.c

266

{ F1207, 7, DCFG_N, 3, { { CH_A, 3, 1 }, { CH_B, 3, 1 } } },

usr/src/uts/intel/io/mc-amd/mcamd_dimmcfg.c

267

{ F1207, 7, DCFG_R4, 1, { { CH_A, 3, 1 }, { CH_B, 3, 1 } } }

usr/src/uts/intel/io/mc-amd/mcamd_dimmcfg.c

303

{ AM2S1g1, 4, DCFG_N, 2, { { CH_B, 0, 0 } } },

usr/src/uts/intel/io/mc-amd/mcamd_dimmcfg.c

304

{ AM2S1g1, 4, DCFG_S4, 1, { { CH_B, 0, 0 } } },

usr/src/uts/intel/io/mc-amd/mcamd_dimmcfg.c

308

{ AM2S1g1, 5, DCFG_N, 2, { { CH_B, 0, 1 } } },

usr/src/uts/intel/io/mc-amd/mcamd_dimmcfg.c

309

{ AM2S1g1, 5, DCFG_S4, 1, { { CH_B, 0, 1 } } },

usr/src/uts/intel/io/mc-amd/mcamd_dimmcfg.c

313

{ AM2, 6, DCFG_N, 3, { { CH_B, 1, 0 } } },

usr/src/uts/intel/io/mc-amd/mcamd_dimmcfg.c

314

{ AM2, 6, DCFG_S4, 1, { { CH_B, 1, 0 } } },

usr/src/uts/intel/io/mc-amd/mcamd_dimmcfg.c

315

{ S1g1, 6, DCFG_N, 3, { { CH_B, 0, 2 } } },

usr/src/uts/intel/io/mc-amd/mcamd_dimmcfg.c

316

{ S1g1, 6, DCFG_S4, 1, { { CH_B, 0, 2 } } },

usr/src/uts/intel/io/mc-amd/mcamd_dimmcfg.c

320

{ AM2, 7, DCFG_N, 3, { { CH_B, 1, 1 } } },

usr/src/uts/intel/io/mc-amd/mcamd_dimmcfg.c

321

{ AM2, 7, DCFG_S4, 1, { { CH_B, 1, 1 } } },

usr/src/uts/intel/io/mc-amd/mcamd_dimmcfg.c

322

{ S1g1, 7, DCFG_N, 3, { { CH_B, 0, 3 } } },

usr/src/uts/intel/io/mc-amd/mcamd_dimmcfg.c

323

{ S1g1, 7, DCFG_S4, 1, { { CH_B, 0, 3 } } }