CHIP_REG_WRITE32
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, &phbamu->inbound_msgaddr0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, &phbcmu->inbound_msgaddr0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, &phbcmu->inbound_doorbell,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, &phbamu->inbound_msgaddr0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, &phbcmu->inbound_msgaddr0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, &phbcmu->inbound_doorbell,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, &phbamu->outbound_intstatus,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle1,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle1,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle1,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle1,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle1,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,
CHIP_REG_WRITE32(acb->reg_mu_acc_handle0,