V_US4_PLUS
{V_US4_PLUS, 0x0, "Cycle_cnt"},
{V_US4_PLUS, 0x1, "Instr_cnt"},
{V_US4_PLUS, 0x2, "Dispatch0_IC_miss"},
{V_US4_PLUS, 0x3, "IU_stat_jmp_correct_pred"},
{V_US4_PLUS, 0x4, "Dispatch0_2nd_br"},
{V_US4_PLUS, 0x5, "Rstall_storeQ"},
{V_US4_PLUS, 0x6, "Rstall_IU_use"},
{V_US4_PLUS, 0x7, "IU_stat_ret_correct_pred"},
{V_US4_PLUS, 0x8, "IC_ref"},
{V_US4_PLUS, 0x9, "DC_rd"},
{V_US4_PLUS, 0xa, "Rstall_FP_use"},
{V_US4_PLUS, 0xb, "SW_pf_instr"},
{V_US4_PLUS, 0xc, "L2_ref"},
{V_US4_PLUS, 0xd, "L2_write_hit_RTO"},
{V_US4_PLUS, 0xe, "L2_snoop_inv_sh"},
{V_US4_PLUS, 0xf, "L2_rd_miss"},
{V_US4_PLUS, 0x10, "PC_rd"},
{V_US4_PLUS, 0x11, "SI_snoop_sh"},
{V_US4_PLUS, 0x12, "SI_ciq_flow_sh"},
{V_US4_PLUS, 0x13, "Re_DC_miss"},
{V_US4_PLUS, 0x14, "SW_count_NOP"},
{V_US4_PLUS, 0x15, "IU_stat_br_miss_taken"},
{V_US4_PLUS, 0x16, "IU_stat_br_count_untaken"},
{V_US4_PLUS, 0x17, "HW_pf_exec"},
{V_US4_PLUS, 0x18, "FA_pipe_completion"},
{V_US4_PLUS, 0x19, "SSM_L3_wb_remote"},
{V_US4_PLUS, 0x1a, "SSM_L3_miss_local"},
{V_US4_PLUS, 0x1b, "SSM_L3_miss_mtag_remote"},
{V_US4_PLUS, 0x1c, "SW_pf_str_trapped"},
{V_US4_PLUS, 0x1d, "SW_pf_PC_installed"},
{V_US4_PLUS, 0x1e, "IPB_to_IC_fill"},
{V_US4_PLUS, 0x1f, "L2_write_miss"},
{V_US4_PLUS, 0x20, "MC_reads_0_sh"},
{V_US4_PLUS, 0x21, "MC_reads_1_sh"},
{V_US4_PLUS, 0x22, "MC_reads_2_sh"},
{V_US4_PLUS, 0x23, "MC_reads_3_sh"},
{V_US4_PLUS, 0x24, "MC_stalls_0_sh"},
{V_US4_PLUS, 0x25, "MC_stalls_2_sh"},
{V_US4_PLUS, 0x26, "L2_hit_other_half"},
{V_US4_PLUS, 0x28, "L3_rd_miss"},
{V_US4_PLUS, 0x29, "Re_L2_miss"},
{V_US4_PLUS, 0x2a, "IC_miss_cancelled"},
{V_US4_PLUS, 0x2b, "DC_wr_miss"},
{V_US4_PLUS, 0x2c, "L3_hit_I_state_sh"},
{V_US4_PLUS, 0x2d, "SI_RTS_src_data"},
{V_US4_PLUS, 0x2e, "L2_IC_miss"},
{V_US4_PLUS, 0x2f, "SSM_new_transaction_sh"},
{V_US4_PLUS, 0x30, "L2_SW_pf_miss"},
{V_US4_PLUS, 0x31, "L2_wb"},
{V_US4_PLUS, 0x32, "L2_wb_sh"},
{V_US4_PLUS, 0x33, "L2_snoop_cb_sh"},
{V_US4_PLUS, 0x0, "Cycle_cnt"},
{V_US4_PLUS, 0x1, "Instr_cnt"},
{V_US4_PLUS, 0x2, "Dispatch0_other"},
{V_US4_PLUS, 0x3, "DC_wr"},
{V_US4_PLUS, 0x4, "Re_DC_missovhd"},
{V_US4_PLUS, 0x5, "Re_FPU_bypass"},
{V_US4_PLUS, 0x6, "L3_write_hit_RTO"},
{V_US4_PLUS, 0x7, "L2L3_snoop_inv_sh"},
{V_US4_PLUS, 0x8, "IC_L2_req"},
{V_US4_PLUS, 0x9, "DC_rd_miss"},
{V_US4_PLUS, 0xa, "L2_hit_I_state_sh"},
{V_US4_PLUS, 0xb, "L3_write_miss_RTO"},
{V_US4_PLUS, 0xc, "L2_miss"},
{V_US4_PLUS, 0xd, "SI_owned_sh"},
{V_US4_PLUS, 0xe, "SI_RTO_src_data"},
{V_US4_PLUS, 0xf, "SW_pf_duplicate"},
{V_US4_PLUS, 0x10, "IU_stat_jmp_mispred"},
{V_US4_PLUS, 0x11, "ITLB_miss"},
{V_US4_PLUS, 0x12, "DTLB_miss"},
{V_US4_PLUS, 0x13, "WC_miss"},
{V_US4_PLUS, 0x14, "IC_fill"},
{V_US4_PLUS, 0x15, "IU_stat_ret_mispred"},
{V_US4_PLUS, 0x16, "Re_L3_miss"},
{V_US4_PLUS, 0x17, "Re_PFQ_full"},
{V_US4_PLUS, 0x18, "PC_soft_hit"},
{V_US4_PLUS, 0x19, "PC_inv"},
{V_US4_PLUS, 0x1a, "PC_hard_hit"},
{V_US4_PLUS, 0x1b, "IC_pf"},
{V_US4_PLUS, 0x1c, "SW_count_NOP"},
{V_US4_PLUS, 0x1d, "IU_stat_br_miss_untaken"},
{V_US4_PLUS, 0x1e, "IU_stat_br_count_taken"},
{V_US4_PLUS, 0x1f, "PC_miss"},
{V_US4_PLUS, 0x20, "MC_writes_0_sh"},
{V_US4_PLUS, 0x21, "MC_writes_1_sh"},
{V_US4_PLUS, 0x22, "MC_writes_2_sh"},
{V_US4_PLUS, 0x23, "MC_writes_3_sh"},
{V_US4_PLUS, 0x24, "MC_stalls_1_sh"},
{V_US4_PLUS, 0x25, "MC_stalls_3_sh"},
{V_US4_PLUS, 0x26, "Re_RAW_miss"},
{V_US4_PLUS, 0x27, "FM_pipe_completion"},
{V_US4_PLUS, 0x28, "SSM_L3_miss_mtag_remote"},
{V_US4_PLUS, 0x29, "SSM_L3_miss_remote"},
{V_US4_PLUS, 0x2a, "SW_pf_exec"},
{V_US4_PLUS, 0x2b, "SW_pf_str_exec"},
{V_US4_PLUS, 0x2c, "SW_pf_dropped"},
{V_US4_PLUS, 0x2d, "SW_pf_L2_installed"},
{V_US4_PLUS, 0x2f, "L2_HW_pf_miss"},
{V_US4_PLUS, 0x31, "L3_miss"},
{V_US4_PLUS, 0x32, "L3_IC_miss"},
{V_US4_PLUS, 0x33, "L3_SW_pf_miss"},
{V_US4_PLUS, 0x34, "L3_hit_other_half"},
{V_US4_PLUS, 0x35, "L3_wb"},
{V_US4_PLUS, 0x36, "L3_wb_sh"},
{V_US4_PLUS, 0x37, "L2L3_snoop_cb_sh"},
case V_US4_PLUS:
case V_US4_PLUS:
case V_US4_PLUS:
V_US4_PLUS /* CPC_ULTRA4_PLUS */