V_P6
{V_P6, 0x43, "data_mem_refs"},
{V_P6, 0x45, "dcu_lines_in"},
{V_P6, 0x46, "dcu_m_lines_in"},
{V_P6, 0x47, "dcu_m_lines_out"},
{V_P6, 0x48, "dcu_miss_outstanding"},
{V_P6, 0x80, "ifu_ifetch"},
{V_P6, 0x81, "ifu_ifetch_miss"},
{V_P6, 0x85, "itlb_miss"},
{V_P6, 0x86, "ifu_mem_stall"},
{V_P6, 0x87, "ild_stall"},
{V_P6, 0x28, "l2_ifetch"},
{V_P6, 0x29, "l2_ld"},
{V_P6, 0x2a, "l2_st"},
{V_P6, 0x24, "l2_lines_in"},
{V_P6, 0x26, "l2_lines_out"},
{V_P6, 0x25, "l2_m_lines_inm"},
{V_P6, 0x27, "l2_m_lines_outm"},
{V_P6, 0x2e, "l2_rqsts"},
{V_P6, 0x21, "l2_ads"},
{V_P6, 0x22, "l2_dbus_busy"},
{V_P6, 0x23, "l2_dbus_busy_rd"},
{V_P6, 0x62, "bus_drdy_clocks"},
{V_P6, 0x63, "bus_lock_clocks"},
{V_P6, 0x60, "bus_req_outstanding"},
{V_P6, 0x65, "bus_tran_brd"},
{V_P6, 0x66, "bus_tran_rfo"},
{V_P6, 0x67, "bus_trans_wb"},
{V_P6, 0x68, "bus_tran_ifetch"},
{V_P6, 0x69, "bus_tran_inval"},
{V_P6, 0x6a, "bus_tran_pwr"},
{V_P6, 0x6b, "bus_trans_p"},
{V_P6, 0x6c, "bus_trans_io"},
{V_P6, 0x6d, "bus_tran_def"},
{V_P6, 0x6e, "bus_tran_burst"},
{V_P6, 0x70, "bus_tran_any"},
{V_P6, 0x6f, "bus_tran_mem"},
{V_P6, 0x64, "bus_data_rcv"},
{V_P6, 0x61, "bus_bnr_drv"},
{V_P6, 0x7a, "bus_hit_drv"},
{V_P6, 0x7b, "bus_hitm_drv"},
{V_P6, 0x7e, "bus_snoop_stall"},
{V_P6, 0xc1, "flops"}, /* 0 only */
{V_P6, 0x10, "fp_comp_ops_exe"}, /* 0 only */
{V_P6, 0x11, "fp_assist"}, /* 1 only */
{V_P6, 0x12, "mul"}, /* 1 only */
{V_P6, 0x13, "div"}, /* 1 only */
{V_P6, 0x14, "cycles_div_busy"}, /* 0 only */
{V_P6, 0x3, "ld_blocks"},
{V_P6, 0x4, "sb_drains"},
{V_P6, 0x5, "misalign_mem_ref"},
{V_P6, 0xc0, "inst_retired"},
{V_P6, 0xc2, "uops_retired"},
{V_P6, 0xd0, "inst_decoder"},
{V_P6, 0xc8, "hw_int_rx"},
{V_P6, 0xc6, "cycles_int_masked"},
{V_P6, 0xc7, "cycles_int_pending_and_masked"},
{V_P6, 0xc4, "br_inst_retired"},
{V_P6, 0xc5, "br_miss_pred_retired"},
{V_P6, 0xc9, "br_taken_retired"},
{V_P6, 0xca, "br_miss_pred_taken_ret"},
{V_P6, 0xe0, "br_inst_decoded"},
{V_P6, 0xe2, "btb_misses"},
{V_P6, 0xe4, "br_bogus"},
{V_P6, 0xe6, "baclears"},
{V_P6, 0xa2, "resource_stalls"},
{V_P6, 0xd2, "partial_rat_stalls"},
{V_P6, 0x6, "segment_reg_loads"},
{V_P6, 0x79, "cpu_clk_unhalted"},
case V_P6:
case V_P6 | V_P6mmx:
case V_P6:
case V_P6 | V_P6mmx:
case V_P6:
case V_P6 | V_P6mmx:
case V_P6:
case V_P6 | V_P6mmx:
V_P6, /* CPC_PENTIUM_PRO */
V_P6 | V_P6mmx, /* CPC_PENTIUM_PRO_MMX */