V_P5mmx
{V_P5mmx, 0x2a, "bus_ownership_latency"},
{V_P5mmx, 0x2b, "mmx_instr_upipe"},
{V_P5mmx, 0x2c, "cache_M_line_sharing"},
{V_P5mmx, 0x2d, "emms_instr"},
{V_P5mmx, 0x2e, "bus_util_processor"},
{V_P5mmx, 0x2f, "sat_mmx_instr"},
{V_P5mmx, 0x30, "clks_not_HLT"},
{V_P5mmx, 0x31, "mmx_data_read"},
{V_P5mmx, 0x32, "clks_fp_stall"},
{V_P5mmx, 0x33, "d1_starv_fifo_0"},
{V_P5mmx, 0x34, "mmx_data_write"},
{V_P5mmx, 0x35, "pipe_flush_wbp"},
{V_P5mmx, 0x36, "mmx_misalign_data_refs"},
{V_P5mmx, 0x37, "rets_pred_incorrect"},
{V_P5mmx, 0x38, "mmx_multiply_unit_interlock"},
{V_P5mmx, 0x39, "rets"},
{V_P5mmx, 0x3a, "btb_false_entries"},
{V_P5mmx, 0x3b, "clocks_stall_full_wb"},
{V_P5mmx, 0x2a, "bus_ownership_transfers"},
{V_P5mmx, 0x2b, "mmx_instr_vpipe"},
{V_P5mmx, 0x2c, "cache_lint_sharing"},
{V_P5mmx, 0x2d, "mmx_fp_transitions"},
{V_P5mmx, 0x2e, "writes_noncache_mem"},
{V_P5mmx, 0x2f, "sats_performed"},
{V_P5mmx, 0x30, "clks_dcache_tlb_miss"},
{V_P5mmx, 0x31, "mmx_data_read_miss"},
{V_P5mmx, 0x32, "taken_br"},
{V_P5mmx, 0x33, "d1_starv_fifo_1"},
{V_P5mmx, 0x34, "mmx_data_write_miss"},
{V_P5mmx, 0x35, "pipe_flush_wbp_wb"},
{V_P5mmx, 0x36, "mmx_pipe_stall_data_read"},
{V_P5mmx, 0x37, "rets_pred"},
{V_P5mmx, 0x38, "movd_movq_stall"},
{V_P5mmx, 0x39, "rsb_overflow"},
{V_P5mmx, 0x3a, "btb_mispred_nt"},
{V_P5mmx, 0x3b, "mmx_stall_write_ME"},
case V_P5 | V_P5mmx:
case V_P5 | V_P5mmx:
case V_P5 | V_P5mmx:
case V_P5 | V_P5mmx:
V_P5 | V_P5mmx, /* CPC_PENTIUM_MMX */