usr/src/uts/common/io/cardbus/cardbus_hp.c

1694

{ "VendorId =", 0, CFG_GET(pci_config_get16), "%s 0x%04x" },

usr/src/uts/common/io/cardbus/cardbus_hp.c

1695

{ "DeviceId =", 2, CFG_GET(pci_config_get16), "%s 0x%04x" },

usr/src/uts/common/io/cardbus/cardbus_hp.c

1696

{ "Command =", 4, CFG_GET(pci_config_get16), "%s 0x%04x" },

usr/src/uts/common/io/cardbus/cardbus_hp.c

1697

{ "Status =", 6, CFG_GET(pci_config_get16), "%s 0x%04x" },

usr/src/uts/common/io/cardbus/cardbus_hp.c

1698

{ "Latency =", 0xd, CFG_GET(pci_config_get8), "%s 0x%02x" },

usr/src/uts/common/io/cardbus/cardbus_hp.c

1699

{ "BASE0 =", 0x10, CFG_GET(pci_config_get32), "%s 0x%08x" },

usr/src/uts/common/io/cardbus/cardbus_hp.c

1700

{ "BASE1 =", 0x14, CFG_GET(pci_config_get32), "%s 0x%08x" },

usr/src/uts/common/io/cardbus/cardbus_hp.c

1701

{ "BASE2 =", 0x18, CFG_GET(pci_config_get32), "%s 0x%08x" },

usr/src/uts/common/io/cardbus/cardbus_hp.c

1702

{ "BASE3 =", 0x1c, CFG_GET(pci_config_get32), "%s 0x%08x" },

usr/src/uts/common/io/cardbus/cardbus_hp.c

1703

{ "BASE4 =", 0x20, CFG_GET(pci_config_get32), "%s 0x%08x" },

usr/src/uts/common/io/cardbus/cardbus_hp.c

1704

{ "CIS Pointer =", 0x28, CFG_GET(pci_config_get32), "%s 0x%08x" },

usr/src/uts/common/io/cardbus/cardbus_hp.c

1705

{ "ILINE =", 0x3c, CFG_GET(pci_config_get8), "%s 0x%02x" },

usr/src/uts/common/io/cardbus/cardbus_hp.c

1706

{ "IPIN =", 0x3d, CFG_GET(pci_config_get8), "%s 0x%02x" },

usr/src/uts/common/io/cardbus/cardbus_hp.c

1711

{ "VendorId =", 0, CFG_GET(pci_config_get16), "%s 0x%04x" },

usr/src/uts/common/io/cardbus/cardbus_hp.c

1712

{ "DeviceId =", 2, CFG_GET(pci_config_get16), "%s 0x%04x" },

usr/src/uts/common/io/cardbus/cardbus_hp.c

1713

{ "Command =", 4, CFG_GET(pci_config_get16), "%s 0x%04x" },

usr/src/uts/common/io/cardbus/cardbus_hp.c

1714

{ "Status =", 6, CFG_GET(pci_config_get16), "%s 0x%04x" },

usr/src/uts/common/io/cardbus/cardbus_hp.c

1715

{ "CacheLineSz =", 0xc, CFG_GET(pci_config_get8), "%s 0x%02x" },

usr/src/uts/common/io/cardbus/cardbus_hp.c

1716

{ "Latency =", 0xd, CFG_GET(pci_config_get8), "%s 0x%02x" },

usr/src/uts/common/io/cardbus/cardbus_hp.c

1717

{ "MemBase Addr=", 0x10, CFG_GET(pci_config_get32), "%s 0x%08x" },

usr/src/uts/common/io/cardbus/cardbus_hp.c

1718

{ "Pri Bus =", 0x18, CFG_GET(pci_config_get8), "%s 0x%02x" },

usr/src/uts/common/io/cardbus/cardbus_hp.c

1719

{ "Sec Bus =", 0x19, CFG_GET(pci_config_get8), "%s 0x%02x" },

usr/src/uts/common/io/cardbus/cardbus_hp.c

1720

{ "Sub Bus =", 0x1a, CFG_GET(pci_config_get8), "%s 0x%02x" },

usr/src/uts/common/io/cardbus/cardbus_hp.c

1721

{ "CBus Latency=", 0x1b, CFG_GET(pci_config_get8), "%s 0x%02x" },

usr/src/uts/common/io/cardbus/cardbus_hp.c

1722

{ "Mem0 Base =", 0x1c, CFG_GET(pci_config_get32), "%s 0x%08x" },

usr/src/uts/common/io/cardbus/cardbus_hp.c

1723

{ "Mem0 Limit =", 0x20, CFG_GET(pci_config_get32), "%s 0x%08x" },

usr/src/uts/common/io/cardbus/cardbus_hp.c

1724

{ "Mem1 Base =", 0x24, CFG_GET(pci_config_get32), "%s 0x%08x" },

usr/src/uts/common/io/cardbus/cardbus_hp.c

1725

{ "Mem1 Limit =", 0x28, CFG_GET(pci_config_get32), "%s 0x%08x" },

usr/src/uts/common/io/cardbus/cardbus_hp.c

1726

{ "I/O0 Base =", 0x2c, CFG_GET(pci_config_get32), "%s 0x%08x" },

usr/src/uts/common/io/cardbus/cardbus_hp.c

1727

{ "I/O0 Limit =", 0x30, CFG_GET(pci_config_get32), "%s 0x%08x" },

usr/src/uts/common/io/cardbus/cardbus_hp.c

1728

{ "I/O1 Base =", 0x34, CFG_GET(pci_config_get32), "%s 0x%08x" },

usr/src/uts/common/io/cardbus/cardbus_hp.c

1729

{ "I/O1 Limit =", 0x38, CFG_GET(pci_config_get32), "%s 0x%08x" },

usr/src/uts/common/io/cardbus/cardbus_hp.c

1730

{ "ILINE =", 0x3c, CFG_GET(pci_config_get8), "%s 0x%02x" },

usr/src/uts/common/io/cardbus/cardbus_hp.c

1731

{ "IPIN =", 0x3d, CFG_GET(pci_config_get8), "%s 0x%02x" },

usr/src/uts/common/io/cardbus/cardbus_hp.c

1732

{ "Bridge Ctrl =", 0x3e, CFG_GET(pci_config_get16), "%s 0x%04x" },

usr/src/uts/common/io/cardbus/cardbus_hp.c

1733

{ "Legacy Addr =", 0x44, CFG_GET(pci_config_get32), "%s 0x%08x" },